From 13c005a8af79a8481879ce099b45a1f98faae165 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 4 Jun 2005 20:50:10 -0400 Subject: shuffle files around for new directory structure --HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032 --- cpu/beta_cpu/rename.hh | 234 ------------------------------------------------- 1 file changed, 234 deletions(-) delete mode 100644 cpu/beta_cpu/rename.hh (limited to 'cpu/beta_cpu/rename.hh') diff --git a/cpu/beta_cpu/rename.hh b/cpu/beta_cpu/rename.hh deleted file mode 100644 index 163177d87..000000000 --- a/cpu/beta_cpu/rename.hh +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -// Todo: -// Fix up trap and barrier handling. -// May want to have different statuses to differentiate the different stall -// conditions. - -#ifndef __CPU_BETA_CPU_SIMPLE_RENAME_HH__ -#define __CPU_BETA_CPU_SIMPLE_RENAME_HH__ - -#include - -#include "base/statistics.hh" -#include "base/timebuf.hh" - -// Will need rename maps for both the int reg file and fp reg file. -// Or change rename map class to handle both. (RegFile handles both.) -template -class SimpleRename -{ - public: - // Typedefs from the Impl. - typedef typename Impl::ISA ISA; - typedef typename Impl::CPUPol CPUPol; - typedef typename Impl::DynInstPtr DynInstPtr; - typedef typename Impl::FullCPU FullCPU; - typedef typename Impl::Params Params; - - typedef typename CPUPol::FetchStruct FetchStruct; - typedef typename CPUPol::DecodeStruct DecodeStruct; - typedef typename CPUPol::RenameStruct RenameStruct; - typedef typename CPUPol::TimeStruct TimeStruct; - - // Typedefs from the CPUPol - typedef typename CPUPol::FreeList FreeList; - typedef typename CPUPol::RenameMap RenameMap; - - // Typedefs from the ISA. - typedef typename ISA::Addr Addr; - - public: - // Rename will block if ROB becomes full or issue queue becomes full, - // or there are no free registers to rename to. - // Only case where rename squashes is if IEW squashes. - enum Status { - Running, - Idle, - Squashing, - Blocked, - Unblocking, - BarrierStall - }; - - private: - Status _status; - - public: - SimpleRename(Params ¶ms); - - void regStats(); - - void setCPU(FullCPU *cpu_ptr); - - void setTimeBuffer(TimeBuffer *tb_ptr); - - void setRenameQueue(TimeBuffer *rq_ptr); - - void setDecodeQueue(TimeBuffer *dq_ptr); - - void setRenameMap(RenameMap *rm_ptr); - - void setFreeList(FreeList *fl_ptr); - - void dumpHistory(); - - void tick(); - - void rename(); - - void squash(); - - private: - void block(); - - inline void unblock(); - - void doSquash(); - - void removeFromHistory(InstSeqNum inst_seq_num); - - inline void renameSrcRegs(DynInstPtr &inst); - - inline void renameDestRegs(DynInstPtr &inst); - - inline int calcFreeROBEntries(); - - inline int calcFreeIQEntries(); - - /** Holds the previous information for each rename. - * Note that often times the inst may have been deleted, so only access - * the pointer for the address and do not dereference it. - */ - struct RenameHistory { - RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, - PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) - : instSeqNum(_instSeqNum), archReg(_archReg), - newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), - placeHolder(false) - { - } - - /** Constructor used specifically for cases where a place holder - * rename history entry is being made. - */ - RenameHistory(InstSeqNum _instSeqNum) - : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), - prevPhysReg(0), placeHolder(true) - { - } - - InstSeqNum instSeqNum; - RegIndex archReg; - PhysRegIndex newPhysReg; - PhysRegIndex prevPhysReg; - bool placeHolder; - }; - - std::list historyBuffer; - - /** CPU interface. */ - FullCPU *cpu; - - // Interfaces to objects outside of rename. - /** Time buffer interface. */ - TimeBuffer *timeBuffer; - - /** Wire to get IEW's output from backwards time buffer. */ - typename TimeBuffer::wire fromIEW; - - /** Wire to get commit's output from backwards time buffer. */ - typename TimeBuffer::wire fromCommit; - - /** Wire to write infromation heading to previous stages. */ - // Might not be the best name as not only decode will read it. - typename TimeBuffer::wire toDecode; - - /** Rename instruction queue. */ - TimeBuffer *renameQueue; - - /** Wire to write any information heading to IEW. */ - typename TimeBuffer::wire toIEW; - - /** Decode instruction queue interface. */ - TimeBuffer *decodeQueue; - - /** Wire to get decode's output from decode queue. */ - typename TimeBuffer::wire fromDecode; - - /** Skid buffer between rename and decode. */ - std::queue skidBuffer; - - /** Rename map interface. */ - SimpleRenameMap *renameMap; - - /** Free list interface. */ - FreeList *freeList; - - /** Delay between iew and rename, in ticks. */ - int iewToRenameDelay; - - /** Delay between decode and rename, in ticks. */ - int decodeToRenameDelay; - - /** Delay between commit and rename, in ticks. */ - unsigned commitToRenameDelay; - - /** Rename width, in instructions. */ - unsigned renameWidth; - - /** Commit width, in instructions. Used so rename knows how many - * instructions might have freed registers in the previous cycle. - */ - unsigned commitWidth; - - /** The instruction that rename is currently on. It needs to have - * persistent state so that when a stall occurs in the middle of a - * group of instructions, it can restart at the proper instruction. - */ - unsigned numInst; - - Stats::Scalar<> renameSquashCycles; - Stats::Scalar<> renameIdleCycles; - Stats::Scalar<> renameBlockCycles; - Stats::Scalar<> renameUnblockCycles; - Stats::Scalar<> renameRenamedInsts; - Stats::Scalar<> renameSquashedInsts; - Stats::Scalar<> renameROBFullEvents; - Stats::Scalar<> renameIQFullEvents; - Stats::Scalar<> renameFullRegistersEvents; - Stats::Scalar<> renameRenamedOperands; - Stats::Scalar<> renameRenameLookups; - Stats::Scalar<> renameHBPlaceHolders; - Stats::Scalar<> renameCommittedMaps; - Stats::Scalar<> renameUndoneMaps; - Stats::Scalar<> renameValidUndoneMaps; -}; - -#endif // __CPU_BETA_CPU_SIMPLE_RENAME_HH__ -- cgit v1.2.3