From 04745696b6b523c5e90c335298099600d4a14a76 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 20 Aug 2004 14:54:07 -0400 Subject: Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches. SConscript: Added new CPU files to build. arch/alpha/isa_desc: Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed. arch/isa_parser.py: Added new CPU exec method. base/statistics.hh: Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up. base/traceflags.py: Added new CPU trace flags. cpu/static_inst.hh: Changed static inst to use a file that defines the execute functions. --HG-- extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519 --- cpu/beta_cpu/rob.cc | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 cpu/beta_cpu/rob.cc (limited to 'cpu/beta_cpu/rob.cc') diff --git a/cpu/beta_cpu/rob.cc b/cpu/beta_cpu/rob.cc new file mode 100644 index 000000000..611cca0ba --- /dev/null +++ b/cpu/beta_cpu/rob.cc @@ -0,0 +1,7 @@ + +#include "cpu/beta_cpu/alpha_dyn_inst.hh" +#include "cpu/beta_cpu/alpha_impl.hh" +#include "cpu/beta_cpu/rob_impl.hh" + +// Force instantiation of InstructionQueue. +template ROB; -- cgit v1.2.3