From 716ceb6c107751fded501f18466a4166b7809e64 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Fri, 11 Aug 2006 17:42:59 -0400
Subject: Code update for CPU models.
arch/alpha/isa_traits.hh:
Add in clear functions.
cpu/base.cc:
cpu/base.hh:
Add in CPU progress event.
cpu/base_dyn_inst.hh:
Mimic normal registers in terms of writing/reading floats.
cpu/checker/cpu.cc:
cpu/checker/cpu.hh:
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
Fix up stuff.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
Bring up to speed with newmem.
cpu/o3/alpha_cpu_builder.cc:
Allow for progress intervals.
cpu/o3/tournament_pred.cc:
Fix up predictor.
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
Fixes.
cpu/ozone/cpu_builder.cc:
Allow progress interval.
cpu/ozone/front_end_impl.hh:
Comment out this message.
cpu/ozone/lw_back_end_impl.hh:
Remove this.
python/m5/objects/BaseCPU.py:
Add progress interval.
python/m5/objects/Root.py:
Allow for stat reset.
sim/serialize.cc:
sim/stat_control.cc:
Add in stats reset.
--HG--
extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e
---
cpu/checker/o3_cpu_builder.cc | 7 +++++++
1 file changed, 7 insertions(+)
(limited to 'cpu/checker/o3_cpu_builder.cc')
diff --git a/cpu/checker/o3_cpu_builder.cc b/cpu/checker/o3_cpu_builder.cc
index 410f91352..496cca779 100644
--- a/cpu/checker/o3_cpu_builder.cc
+++ b/cpu/checker/o3_cpu_builder.cc
@@ -58,6 +58,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
+ Param<Tick> progress_interval;
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
@@ -75,6 +76,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
Param<bool> defer_registration;
Param<bool> exitOnError;
+ Param<bool> updateOnError;
Param<bool> function_trace;
Param<Tick> function_trace_start;
@@ -90,6 +92,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
+ INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
@@ -108,6 +111,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(exitOnError, "exit on error"),
+ INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace")
@@ -124,6 +128,7 @@ CREATE_SIM_OBJECT(O3Checker)
params->max_loads_any_thread = 0;
params->max_loads_all_threads = 0;
params->exitOnError = exitOnError;
+ params->updateOnError = updateOnError;
params->deferRegistration = defer_registration;
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
@@ -135,6 +140,8 @@ CREATE_SIM_OBJECT(O3Checker)
temp = max_insts_all_threads;
temp = max_loads_any_thread;
temp = max_loads_all_threads;
+ Tick temp2 = progress_interval;
+ temp2++;
BaseMem *cache = icache;
cache = dcache;
--
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