From 83d32482dc126d028399ca6701642047f28276dd Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 18 Oct 2003 21:21:14 -0700 Subject: Add comment to elaborate on store-conditional result code (and remove stale reference to machine.def). arch/alpha/isa_desc: Add comment describing store-conditional result code cpu/exec_context.hh: update comments --HG-- extra : convert_revision : ac59e0ad7a9440cb6656617fdf05495b59c68f55 --- cpu/exec_context.hh | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'cpu/exec_context.hh') diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index ddfc53684..4a2688f1c 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -218,7 +218,7 @@ class ExecContext cregs = &req->xc->regs.miscRegs; if (req->flags & UNCACHEABLE) { - // Don't update result register (see machine.def) + // Don't update result register (see stq_c in isa_desc) req->result = 2; req->xc->storeCondFailures = 0;//Needed? [RGD] } else { @@ -239,12 +239,11 @@ class ExecContext } } - // Need to clear any locked flags on other proccessors for this - // address - // Only do this for succsful Store Conditionals and all other - // stores (WH64?) - // Unsuccesful Store Conditionals would have returned above, - // and wouldn't fall through + // Need to clear any locked flags on other proccessors for + // this address. Only do this for succsful Store Conditionals + // and all other stores (WH64?). Unsuccessful Store + // Conditionals would have returned above, and wouldn't fall + // through. for (int i = 0; i < system->xcvec.size(); i++){ cregs = &system->xcvec[i]->regs.miscRegs; if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { -- cgit v1.2.3