From 51f19f2e28a30054d4a9cc06b059b602e17e504f Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Thu, 28 Sep 2006 00:09:27 -0400
Subject: Minor changes plus updates to O3.

cpu/base.cc:
    Have output message regardless of build.
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
    Be sure to include all parameters.
cpu/o3/cpu.cc:
    IEW also needs to switch out.
cpu/o3/iew_impl.hh:
    Handle stores with faults properly.
cpu/o3/inst_queue_impl.hh:
    Switch out properly, handle squashing properly.
cpu/o3/lsq_unit_impl.hh:
    Minor fixes.
cpu/o3/mem_dep_unit_impl.hh:
    Make sure mem dep unit is switched out properly.
cpu/o3/rename_impl.hh:
    Switch out fix.

--HG--
extra : convert_revision : b94deb83f724225c01166c84a1b3fdd3543cbe9a
---
 cpu/o3/lsq_unit_impl.hh | 61 +++++++------------------------------------------
 1 file changed, 8 insertions(+), 53 deletions(-)

(limited to 'cpu/o3/lsq_unit_impl.hh')

diff --git a/cpu/o3/lsq_unit_impl.hh b/cpu/o3/lsq_unit_impl.hh
index 7086c381e..f75a41cfe 100644
--- a/cpu/o3/lsq_unit_impl.hh
+++ b/cpu/o3/lsq_unit_impl.hh
@@ -198,62 +198,12 @@ void
 LSQUnit<Impl>::switchOut()
 {
     switchedOut = true;
-    for (int i = 0; i < loadQueue.size(); ++i)
+    for (int i = 0; i < loadQueue.size(); ++i) {
+        assert(!loadQueue[i]);
         loadQueue[i] = NULL;
+    }
 
     assert(storesToWB == 0);
-
-    while (storesToWB > 0 &&
-           storeWBIdx != storeTail &&
-           storeQueue[storeWBIdx].inst &&
-           storeQueue[storeWBIdx].canWB) {
-
-        if (storeQueue[storeWBIdx].size == 0 ||
-            storeQueue[storeWBIdx].inst->isDataPrefetch() ||
-            storeQueue[storeWBIdx].committed ||
-            storeQueue[storeWBIdx].req->flags & LOCKED) {
-            incrStIdx(storeWBIdx);
-
-            continue;
-        }
-
-        assert(storeQueue[storeWBIdx].req);
-        assert(!storeQueue[storeWBIdx].committed);
-
-        MemReqPtr req = storeQueue[storeWBIdx].req;
-        storeQueue[storeWBIdx].committed = true;
-
-        req->cmd = Write;
-        req->completionEvent = NULL;
-        req->time = curTick;
-        assert(!req->data);
-        req->data = new uint8_t[64];
-        memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
-
-        DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
-                "to Addr:%#x, data:%#x [sn:%lli]\n",
-                storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
-                req->paddr, *(req->data),
-                storeQueue[storeWBIdx].inst->seqNum);
-
-        switch(storeQueue[storeWBIdx].size) {
-          case 1:
-            cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
-            break;
-          case 2:
-            cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data);
-            break;
-          case 4:
-            cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data);
-            break;
-          case 8:
-            cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data);
-            break;
-          default:
-            panic("Unexpected store size!\n");
-        }
-        incrStIdx(storeWBIdx);
-    }
 }
 
 template<class Impl>
@@ -439,6 +389,11 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
     if (load_fault != NoFault) {
         // Send this instruction to commit, also make sure iew stage
         // realizes there is activity.
+        // Mark it as executed unless it is an uncached load that
+        // needs to hit the head of commit.
+        if (!(inst->req->flags & UNCACHEABLE) || inst->isAtCommit()) {
+            inst->setExecuted();
+        }
         iewStage->instToCommit(inst);
         iewStage->activityThisCycle();
     }
-- 
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