From 2939a7089ad89e38b24f96143dbd3c4292ac0287 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Feb 2006 00:16:44 -0500 Subject: byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions. arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: Added the endianness namespace. This may change. cpu/exec_context.hh: Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution. cpu/o3/alpha_cpu.hh: Forced LittleEndianness, for lack of a better solution. cpu/o3/alpha_cpu_impl.hh: Cleared away some commented out code. cpu/o3/fetch_impl.hh: Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution. cpu/simple/cpu.cc: Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine. dev/disk_image.cc: Changed the include path of byteswap.hh kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution. sim/system.cc: Forced LittleEndianness for lack of a better solution. --HG-- extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206 --- cpu/o3/alpha_cpu.hh | 4 ++-- cpu/o3/alpha_cpu_impl.hh | 3 --- cpu/o3/fetch_impl.hh | 4 ++-- 3 files changed, 4 insertions(+), 7 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index cba57d189..164da4968 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -220,7 +220,7 @@ class AlphaFullCPU : public FullO3CPU Fault error; error = this->mem->read(req, data); - data = gtoh(data); + data = LittleEndianGuest::gtoh(data); return error; } @@ -277,7 +277,7 @@ class AlphaFullCPU : public FullO3CPU #endif - return this->mem->write(req, (T)htog(data)); + return this->mem->write(req, (T)LittleEndianGuest::htog(data)); } template diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 2a764740b..3b16975a9 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -42,9 +42,6 @@ #if FULL_SYSTEM #include "arch/alpha/osfpal.hh" #include "arch/alpha/isa_traits.hh" -//#include "arch/alpha/ev5.hh" - -//using namespace EV5; #endif template diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh index c943fd36a..1a8411cc1 100644 --- a/cpu/o3/fetch_impl.hh +++ b/cpu/o3/fetch_impl.hh @@ -30,7 +30,7 @@ #define OPCODE(X) (X >> 26) & 0x3f -#include "arch/alpha/byte_swap.hh" +#include "sim/byteswap.hh" #include "cpu/exetrace.hh" #include "mem/base_mem.hh" #include "mem/mem_interface.hh" @@ -535,7 +535,7 @@ SimpleFetch::fetch() assert(offset <= cacheBlkSize - instSize); // Get the instruction from the array of the cache line. - inst = gtoh(*reinterpret_cast + inst = LittleEndianGuest::gtoh(*reinterpret_cast (&cacheData[offset])); // Create a new DynInst from the instruction fetched. -- cgit v1.2.3 From 82f2ae56ed27b25f163db5ac4f2ccf0612640b07 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Feb 2006 01:03:55 -0500 Subject: Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh SConscript: Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content. arch/alpha/isa_traits.hh: Added alpha's endianness to it's isa_traits.hh arch/mips/isa_traits.hh: Added MIPS endianness to it's isa_traits.hh arch/sparc/isa_traits.hh: Added SPARCs endianess to it's isa_traits.hh build/SConstruct: Added MIPS as a valid architecture cpu/exec_context.hh: Included arch/isa_traits.hh to bring in the endianness of the system. cpu/o3/alpha_cpu.hh: Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness cpu/o3/fetch_impl.hh: kern/freebsd/freebsd_system.cc: Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness. sim/system.cc: Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian. --HG-- extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007 --- cpu/o3/alpha_cpu.hh | 6 ++++-- cpu/o3/fetch_impl.hh | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index 164da4968..1e1a72af0 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -33,6 +33,8 @@ #define __CPU_O3_CPU_ALPHA_FULL_CPU_HH__ #include "cpu/o3/cpu.hh" +#include "arch/isa_traits.hh" +#include "sim/byteswap.hh" template class AlphaFullCPU : public FullO3CPU @@ -220,7 +222,7 @@ class AlphaFullCPU : public FullO3CPU Fault error; error = this->mem->read(req, data); - data = LittleEndianGuest::gtoh(data); + data = gtoh(data); return error; } @@ -277,7 +279,7 @@ class AlphaFullCPU : public FullO3CPU #endif - return this->mem->write(req, (T)LittleEndianGuest::htog(data)); + return this->mem->write(req, (T)::htog(data)); } template diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh index 1a8411cc1..cd1ed1351 100644 --- a/cpu/o3/fetch_impl.hh +++ b/cpu/o3/fetch_impl.hh @@ -29,7 +29,7 @@ // Remove this later; used only for debugging. #define OPCODE(X) (X >> 26) & 0x3f - +#include "arch/isa_traits.hh" #include "sim/byteswap.hh" #include "cpu/exetrace.hh" #include "mem/base_mem.hh" @@ -535,7 +535,7 @@ SimpleFetch::fetch() assert(offset <= cacheBlkSize - instSize); // Get the instruction from the array of the cache line. - inst = LittleEndianGuest::gtoh(*reinterpret_cast + inst = gtoh(*reinterpret_cast (&cacheData[offset])); // Create a new DynInst from the instruction fetched. -- cgit v1.2.3 From fb7899aa681001d2af7837eae7bf0e19fd3e1b02 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 10 Feb 2006 14:21:32 -0500 Subject: fix problems on darwin/*BSD for syscall emulation mode arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: fixup for bsd hosts. Some headers are included by default which means that more variables need TGT_ prefixes and there isn't a stat call (everything is a stat64 call) so we have to work around that a bit base/intmath.hh: base/socket.cc: this is no longer needed with mac os 10.4 cpu/inst_seq.hh: just use a uint64_t instead of long long cpu/o3/inst_queue_impl.hh: I much cleaner way to get max int sim/syscall_emul.hh: fix stat64 problems on *BSD --HG-- extra : convert_revision : 9eef5f896e083ae1774e818a9765dd83e0305942 --- cpu/o3/inst_queue_impl.hh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'cpu/o3') diff --git a/cpu/o3/inst_queue_impl.hh b/cpu/o3/inst_queue_impl.hh index 2221ba456..048dc7c00 100644 --- a/cpu/o3/inst_queue_impl.hh +++ b/cpu/o3/inst_queue_impl.hh @@ -34,6 +34,7 @@ // but probably is more flexible to actually add in a delay parameter than // just running it backwards. +#include #include #include "sim/root.hh" @@ -42,7 +43,7 @@ // Either compile error or max int due to sign extension. // Hack to avoid compile warnings. -const InstSeqNum MaxInstSeqNum = 0 - 1; +const InstSeqNum MaxInstSeqNum = std::numeric_limits::max(); template InstructionQueue::InstructionQueue(Params ¶ms) -- cgit v1.2.3 From 10c79efe556697ebbed74c82214b5505b405da5b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 16 Feb 2006 01:22:51 -0500 Subject: Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA. SConscript: The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away. arch/alpha/alpha_memory.cc: Changed Fault to Fault * and took the underscores out of fault names. arch/alpha/alpha_memory.hh: Changed Fault to Fault *. Also, added an include for the alpha faults. arch/alpha/ev5.cc: Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names. arch/alpha/isa/decoder.isa: Changed Fault to Fault * and took the underscores out fault names. arch/alpha/isa/fp.isa: Changed Fault to Fault *, and took the underscores out of fault names. arch/alpha/isa/main.isa: Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files. arch/alpha/isa/mem.isa: Changed Fault to Fault * and removed underscores from fault names. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: cpu/exec_context.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: dev/alpha_console.cc: dev/ide_ctrl.cc: dev/isa_fake.cc: dev/pciconfigall.cc: dev/pcidev.cc: dev/pcidev.hh: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Changed Fault to Fault *, and removed underscores from fault names. arch/alpha/isa_traits.hh: Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed. cpu/base_dyn_inst.cc: Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault. cpu/base_dyn_inst.hh: Changed Fault to Fault * and took the underscores out of the fault names. cpu/exec_context.cc: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/fetch.hh: dev/alpha_console.hh: dev/baddev.hh: dev/ide_ctrl.hh: dev/isa_fake.hh: dev/ns_gige.hh: dev/pciconfigall.hh: dev/sinic.hh: dev/tsunami_cchip.hh: dev/tsunami_io.hh: dev/tsunami_pchip.hh: dev/uart.hh: dev/uart8250.hh: Changed Fault to Fault *. cpu/o3/alpha_cpu.hh: Changed Fault to Fault *, removed underscores from fault names. cpu/o3/alpha_cpu_impl.hh: Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away. cpu/o3/commit_impl.hh: cpu/o3/fetch_impl.hh: dev/baddev.cc: Changed Fault to Fault *, and removed underscores from the fault names. cpu/o3/regfile.hh: Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names. cpu/simple/cpu.hh: Changed Fault to Fault * dev/ns_gige.cc: Changed Fault to Fault *, and removdd underscores from fault names. dev/sinic.cc: Changed Fault to Fault *, and removed the underscores from fault names. dev/uart8250.cc: Chanted Fault to Fault *, and removed underscores from fault names. kern/kernel_stats.cc: Removed underscores from fault names, and from NumFaults. kern/kernel_stats.hh: Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally. sim/faults.cc: This allocates the system wide faults. sim/faults.hh: This declares the system wide faults. sim/syscall_emul.cc: sim/syscall_emul.hh: Removed the underscores from fault names. --HG-- rename : arch/alpha/faults.cc => sim/faults.cc rename : arch/alpha/faults.hh => sim/faults.hh extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d --- cpu/o3/alpha_cpu.hh | 38 +++++++++++++++++++------------------- cpu/o3/alpha_cpu_impl.hh | 26 +++++++++++++------------- cpu/o3/alpha_dyn_inst.hh | 14 +++++++------- cpu/o3/alpha_dyn_inst_impl.hh | 8 ++++---- cpu/o3/commit_impl.hh | 4 ++-- cpu/o3/fetch.hh | 2 +- cpu/o3/fetch_impl.hh | 14 +++++++------- cpu/o3/regfile.hh | 19 ++++++++++--------- 8 files changed, 63 insertions(+), 62 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index 1e1a72af0..606f9fa0a 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -62,23 +62,23 @@ class AlphaFullCPU : public FullO3CPU // void clear_interrupt(int int_num, int index); // void clear_interrupts(); - Fault translateInstReq(MemReqPtr &req) + Fault * translateInstReq(MemReqPtr &req) { return itb->translate(req); } - Fault translateDataReadReq(MemReqPtr &req) + Fault * translateDataReadReq(MemReqPtr &req) { return dtb->translate(req, false); } - Fault translateDataWriteReq(MemReqPtr &req) + Fault * translateDataWriteReq(MemReqPtr &req) { return dtb->translate(req, true); } #else - Fault dummyTranslation(MemReqPtr &req) + Fault * dummyTranslation(MemReqPtr &req) { #if 0 assert((req->vaddr >> 48 & 0xffff) == 0); @@ -87,20 +87,20 @@ class AlphaFullCPU : public FullO3CPU // put the asid in the upper 16 bits of the paddr req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; - return No_Fault; + return NoFault; } - Fault translateInstReq(MemReqPtr &req) + Fault * translateInstReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault translateDataReadReq(MemReqPtr &req) + Fault * translateDataReadReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault translateDataWriteReq(MemReqPtr &req) + Fault * translateDataWriteReq(MemReqPtr &req) { return dummyTranslation(req); } @@ -135,16 +135,16 @@ class AlphaFullCPU : public FullO3CPU // look like. #if FULL_SYSTEM uint64_t *getIpr(); - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); + uint64_t readIpr(int idx, Fault * &fault); + Fault * setIpr(int idx, uint64_t val); int readIntrFlag(); void setIntrFlag(int val); - Fault hwrei(); + Fault * hwrei(); bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); } bool inPalMode(uint64_t PC) { return AlphaISA::PcPAL(PC); } - void trap(Fault fault); + void trap(Fault * fault); bool simPalCheck(int palFunc); void processInterrupts(); @@ -197,7 +197,7 @@ class AlphaFullCPU : public FullO3CPU bool palShadowEnabled; // Not sure this is used anywhere. - void intr_post(RegFile *regs, Fault fault, Addr pc); + void intr_post(RegFile *regs, Fault * fault, Addr pc); // Actually used within exec files. Implement properly. void swapPALShadow(bool use_shadow); // Called by CPU constructor. Can implement as I please. @@ -210,7 +210,7 @@ class AlphaFullCPU : public FullO3CPU template - Fault read(MemReqPtr &req, T &data) + Fault * read(MemReqPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) if (req->flags & LOCKED) { @@ -220,20 +220,20 @@ class AlphaFullCPU : public FullO3CPU } #endif - Fault error; + Fault * error; error = this->mem->read(req, data); data = gtoh(data); return error; } template - Fault read(MemReqPtr &req, T &data, int load_idx) + Fault * read(MemReqPtr &req, T &data, int load_idx) { return this->iew.ldstQueue.read(req, data, load_idx); } template - Fault write(MemReqPtr &req, T &data) + Fault * write(MemReqPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) @@ -259,7 +259,7 @@ class AlphaFullCPU : public FullO3CPU << "on cpu " << this->cpu_id << std::endl; } - return No_Fault; + return NoFault; } else req->xc->storeCondFailures = 0; } @@ -283,7 +283,7 @@ class AlphaFullCPU : public FullO3CPU } template - Fault write(MemReqPtr &req, T &data, int store_idx) + Fault * write(MemReqPtr &req, T &data, int store_idx) { return this->iew.ldstQueue.write(req, data, store_idx); } diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 3b16975a9..408676331 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -246,13 +246,13 @@ AlphaFullCPU::getIpr() template uint64_t -AlphaFullCPU::readIpr(int idx, Fault &fault) +AlphaFullCPU::readIpr(int idx, Fault * &fault) { return this->regFile.readIpr(idx, fault); } template -Fault +Fault * AlphaFullCPU::setIpr(int idx, uint64_t val) { return this->regFile.setIpr(idx, val); @@ -274,13 +274,13 @@ AlphaFullCPU::setIntrFlag(int val) // Can force commit stage to squash and stuff. template -Fault +Fault * AlphaFullCPU::hwrei() { uint64_t *ipr = getIpr(); if (!inPalMode()) - return Unimplemented_Opcode_Fault; + return UnimplementedOpcodeFault; setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); @@ -292,7 +292,7 @@ AlphaFullCPU::hwrei() this->checkInterrupts = true; // FIXME: XXX check for interrupts? XXX - return No_Fault; + return NoFault; } template @@ -323,28 +323,28 @@ AlphaFullCPU::simPalCheck(int palFunc) // stage. template void -AlphaFullCPU::trap(Fault fault) +AlphaFullCPU::trap(Fault * fault) { // Keep in mind that a trap may be initiated by fetch if there's a TLB // miss uint64_t PC = this->commit.readCommitPC(); - DPRINTF(Fault, "Fault %s\n", FaultName(fault)); - this->recordEvent(csprintf("Fault %s", FaultName(fault))); + DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name"); + this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name")); // kernelStats.fault(fault); - if (fault == Arithmetic_Fault) + if (fault == ArithmeticFault) panic("Arithmetic traps are unimplemented!"); typename AlphaISA::InternalProcReg *ipr = getIpr(); // exception restart address - Get the commit PC - if (fault != Interrupt_Fault || !inPalMode(PC)) + if (fault != InterruptFault || !inPalMode(PC)) ipr[AlphaISA::IPR_EXC_ADDR] = PC; - if (fault == Pal_Fault || fault == Arithmetic_Fault /* || - fault == Interrupt_Fault && !PC_PAL(regs.pc) */) { + if (fault == PalFault || fault == ArithmeticFault /* || + fault == InterruptFault && !PC_PAL(regs.pc) */) { // traps... skip faulting instruction ipr[AlphaISA::IPR_EXC_ADDR] += 4; } @@ -353,7 +353,7 @@ AlphaFullCPU::trap(Fault fault) swapPALShadow(true); this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] + - AlphaISA::fault_addr[fault] ); + AlphaISA::fault_addr(fault) ); this->regFile.setNextPC(PC + sizeof(MachInst)); } diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index bb90bf21a..77dcbaf74 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -74,7 +74,7 @@ class AlphaDynInst : public BaseDynInst AlphaDynInst(StaticInstPtr &_staticInst); /** Executes the instruction.*/ - Fault execute() + Fault * execute() { return this->fault = this->staticInst->execute(this, this->traceData); } @@ -87,13 +87,13 @@ class AlphaDynInst : public BaseDynInst void setFpcr(uint64_t val); #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); - Fault hwrei(); + uint64_t readIpr(int idx, Fault * &fault); + Fault * setIpr(int idx, uint64_t val); + Fault * hwrei(); int readIntrFlag(); void setIntrFlag(int val); bool inPalMode(); - void trap(Fault fault); + void trap(Fault * fault); bool simPalCheck(int palFunc); #else void syscall(); @@ -220,12 +220,12 @@ class AlphaDynInst : public BaseDynInst } public: - Fault calcEA() + Fault * calcEA() { return this->staticInst->eaCompInst()->execute(this, this->traceData); } - Fault memAccess() + Fault * memAccess() { return this->staticInst->memAccInst()->execute(this, this->traceData); } diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh index d1ebb812d..b20af48cd 100644 --- a/cpu/o3/alpha_dyn_inst_impl.hh +++ b/cpu/o3/alpha_dyn_inst_impl.hh @@ -98,20 +98,20 @@ AlphaDynInst::setFpcr(uint64_t val) #if FULL_SYSTEM template uint64_t -AlphaDynInst::readIpr(int idx, Fault &fault) +AlphaDynInst::readIpr(int idx, Fault * &fault) { return this->cpu->readIpr(idx, fault); } template -Fault +Fault * AlphaDynInst::setIpr(int idx, uint64_t val) { return this->cpu->setIpr(idx, val); } template -Fault +Fault * AlphaDynInst::hwrei() { return this->cpu->hwrei(); @@ -140,7 +140,7 @@ AlphaDynInst::inPalMode() template void -AlphaDynInst::trap(Fault fault) +AlphaDynInst::trap(Fault * fault) { this->cpu->trap(fault); } diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh index dc0986772..540f16b78 100644 --- a/cpu/o3/commit_impl.hh +++ b/cpu/o3/commit_impl.hh @@ -393,9 +393,9 @@ SimpleCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) } // Check if the instruction caused a fault. If so, trap. - Fault inst_fault = head_inst->getFault(); + Fault * inst_fault = head_inst->getFault(); - if (inst_fault != No_Fault && inst_fault != Fake_Mem_Fault) { + if (inst_fault != NoFault && inst_fault != FakeMemFault) { if (!head_inst->isNop()) { #if FULL_SYSTEM cpu->trap(inst_fault); diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh index 24e445f0b..5443d274e 100644 --- a/cpu/o3/fetch.hh +++ b/cpu/o3/fetch.hh @@ -123,7 +123,7 @@ class SimpleFetch * @param fetch_PC The PC address that is being fetched from. * @return Any fault that occured. */ - Fault fetchCacheLine(Addr fetch_PC); + Fault * fetchCacheLine(Addr fetch_PC); inline void doSquash(const Addr &new_PC); diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh index cd1ed1351..e8d333ed4 100644 --- a/cpu/o3/fetch_impl.hh +++ b/cpu/o3/fetch_impl.hh @@ -221,7 +221,7 @@ SimpleFetch::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC) } template -Fault +Fault * SimpleFetch::fetchCacheLine(Addr fetch_PC) { // Check if the instruction exists within the cache. @@ -236,7 +236,7 @@ SimpleFetch::fetchCacheLine(Addr fetch_PC) unsigned flags = 0; #endif // FULL_SYSTEM - Fault fault = No_Fault; + Fault * fault = NoFault; // Align the fetch PC so it's at the start of a cache block. fetch_PC = icacheBlockAlignPC(fetch_PC); @@ -258,7 +258,7 @@ SimpleFetch::fetchCacheLine(Addr fetch_PC) // If translation was successful, attempt to read the first // instruction. - if (fault == No_Fault) { + if (fault == NoFault) { DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); fault = cpu->mem->read(memReq, cacheData); // This read may change when the mem interface changes. @@ -268,7 +268,7 @@ SimpleFetch::fetchCacheLine(Addr fetch_PC) // Now do the timing access to see whether or not the instruction // exists within the cache. - if (icacheInterface && fault == No_Fault) { + if (icacheInterface && fault == NoFault) { DPRINTF(Fetch, "Fetch: Doing timing memory access.\n"); memReq->completionEvent = NULL; @@ -468,7 +468,7 @@ SimpleFetch::fetch() Addr fetch_PC = cpu->readPC(); // Fault code for memory access. - Fault fault = No_Fault; + Fault * fault = NoFault; // If returning from the delay of a cache miss, then update the status // to running, otherwise do the cache access. Possibly move this up @@ -506,7 +506,7 @@ SimpleFetch::fetch() unsigned offset = fetch_PC & cacheBlkMask; unsigned fetched; - if (fault == No_Fault) { + if (fault == NoFault) { // If the read of the first instruction was successful, then grab the // instructions from the rest of the cache line and put them into the // queue heading to decode. @@ -582,7 +582,7 @@ SimpleFetch::fetch() // Or might want to leave setting the PC to the main CPU, with fetch // only changing the nextPC (will require correct determination of // next PC). - if (fault == No_Fault) { + if (fault == NoFault) { DPRINTF(Fetch, "Fetch: Setting PC to %08p.\n", next_PC); cpu->setPC(next_PC); cpu->setNextPC(next_PC + instSize); diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 4d47b8f9c..5aafd5495 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -32,6 +32,7 @@ // @todo: Destructor #include "arch/alpha/isa_traits.hh" +#include "arch/alpha/faults.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/o3/comm.hh" @@ -211,8 +212,8 @@ class PhysRegFile } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); + uint64_t readIpr(int idx, Fault * &fault); + Fault * setIpr(int idx, uint64_t val); InternalProcReg *getIpr() { return ipr; } int readIntrFlag() { return intrflag; } void setIntrFlag(int val) { intrflag = val; } @@ -275,7 +276,7 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs, //the DynInst level. template uint64_t -PhysRegFile::readIpr(int idx, Fault &fault) +PhysRegFile::readIpr(int idx, Fault * &fault) { uint64_t retval = 0; // return value, default 0 @@ -368,12 +369,12 @@ PhysRegFile::readIpr(int idx, Fault &fault) case ISA::IPR_DTB_IAP: case ISA::IPR_ITB_IA: case ISA::IPR_ITB_IAP: - fault = Unimplemented_Opcode_Fault; + fault = UnimplementedOpcodeFault; break; default: // invalid IPR - fault = Unimplemented_Opcode_Fault; + fault = UnimplementedOpcodeFault; break; } @@ -383,7 +384,7 @@ PhysRegFile::readIpr(int idx, Fault &fault) extern int break_ipl; template -Fault +Fault * PhysRegFile::setIpr(int idx, uint64_t val) { uint64_t old; @@ -521,7 +522,7 @@ PhysRegFile::setIpr(int idx, uint64_t val) case ISA::IPR_ITB_PTE_TEMP: case ISA::IPR_DTB_PTE_TEMP: // read-only registers - return Unimplemented_Opcode_Fault; + return UnimplementedOpcodeFault; case ISA::IPR_HWINT_CLR: case ISA::IPR_SL_XMIT: @@ -623,11 +624,11 @@ PhysRegFile::setIpr(int idx, uint64_t val) default: // invalid IPR - return Unimplemented_Opcode_Fault; + return UnimplementedOpcodeFault; } // no error... - return No_Fault; + return NoFault; } #endif // #if FULL_SYSTEM -- cgit v1.2.3 From d6a330ebb949b6cd63195d44e5a4304e2fd3378e Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 16 Feb 2006 14:55:15 -0500 Subject: Remove fake fault. Switch fault pointers to const pointers to prevent them from accidentally being changed. Fix some coding style. arch/alpha/ev5.cc: cpu/o3/commit_impl.hh: kern/kernel_stats.hh: Remove fake fault. arch/alpha/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/alpha/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. sim/faults.cc: sim/faults.hh: Remove fake fault, change pointers to const pointers. --HG-- extra : convert_revision : 01d4600e0d4bdc1d177b32edebc78f86a1bbfe2e --- cpu/o3/commit_impl.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/o3') diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh index 540f16b78..47b4dfd00 100644 --- a/cpu/o3/commit_impl.hh +++ b/cpu/o3/commit_impl.hh @@ -395,7 +395,7 @@ SimpleCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) // Check if the instruction caused a fault. If so, trap. Fault * inst_fault = head_inst->getFault(); - if (inst_fault != NoFault && inst_fault != FakeMemFault) { + if (inst_fault != NoFault) { if (!head_inst->isNop()) { #if FULL_SYSTEM cpu->trap(inst_fault); -- cgit v1.2.3 From 463aa6d49d49ba9c383f07207df57bad75c58ec9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 19 Feb 2006 02:34:37 -0500 Subject: Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45 --- cpu/o3/2bit_local_pred.hh | 4 +- cpu/o3/alpha_cpu.hh | 4 +- cpu/o3/alpha_cpu_impl.hh | 4 +- cpu/o3/alpha_dyn_inst.hh | 33 +++-- cpu/o3/alpha_dyn_inst_impl.hh | 2 +- cpu/o3/alpha_impl.hh | 5 +- cpu/o3/bpred_unit.hh | 2 + cpu/o3/bpred_unit_impl.hh | 2 + cpu/o3/btb.cc | 2 + cpu/o3/btb.hh | 4 +- cpu/o3/commit.hh | 1 - cpu/o3/cpu.cc | 18 +-- cpu/o3/cpu.hh | 5 +- cpu/o3/decode.hh | 3 +- cpu/o3/fetch.hh | 6 +- cpu/o3/free_list.hh | 2 +- cpu/o3/iew.hh | 1 - cpu/o3/iew_impl.hh | 2 +- cpu/o3/ras.hh | 4 +- cpu/o3/regfile.hh | 290 +++++++++++++++++++++--------------------- cpu/o3/rename.hh | 4 +- cpu/o3/rename_map.hh | 4 + cpu/o3/rob.hh | 2 + cpu/o3/store_set.hh | 4 +- cpu/o3/tournament_pred.hh | 4 +- 25 files changed, 215 insertions(+), 197 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh index a97ce455c..78efe1e43 100644 --- a/cpu/o3/2bit_local_pred.hh +++ b/cpu/o3/2bit_local_pred.hh @@ -30,11 +30,13 @@ #define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/o3/sat_counter.hh" class DefaultBP { + protected: + typedef TheISA::Addr Addr; public: /** * Default branch predictor constructor. diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index 606f9fa0a..bf3556b8e 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -39,8 +39,10 @@ template class AlphaFullCPU : public FullO3CPU { + protected: + typedef AlphaISA::Addr Addr; + typedef TheISA::IntReg IntReg; public: - typedef typename Impl::ISA AlphaISA; typedef typename Impl::Params Params; public: diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 408676331..6736cf9bc 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -282,7 +282,7 @@ AlphaFullCPU::hwrei() if (!inPalMode()) return UnimplementedOpcodeFault; - setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); + this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); // kernelStats.hwrei(); @@ -337,7 +337,7 @@ AlphaFullCPU::trap(Fault * fault) if (fault == ArithmeticFault) panic("Arithmetic traps are unimplemented!"); - typename AlphaISA::InternalProcReg *ipr = getIpr(); + AlphaISA::InternalProcReg *ipr = getIpr(); // exception restart address - Get the commit PC if (fault != InterruptFault || !inPalMode(PC)) diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index 77dcbaf74..22be2aae5 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -48,21 +48,18 @@ class AlphaDynInst : public BaseDynInst /** Typedef for the CPU. */ typedef typename Impl::FullCPU FullCPU; - /** Typedef to get the ISA. */ - typedef typename Impl::ISA ISA; - /** Binary machine instruction type. */ - typedef typename ISA::MachInst MachInst; + typedef TheISA::MachInst MachInst; /** Memory address type. */ - typedef typename ISA::Addr Addr; + typedef TheISA::Addr Addr; /** Logical register index type. */ - typedef typename ISA::RegIndex RegIndex; + typedef TheISA::RegIndex RegIndex; /** Integer register index type. */ - typedef typename ISA::IntReg IntReg; + typedef TheISA::IntReg IntReg; enum { - MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs - MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs + MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs + MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs }; public: @@ -71,7 +68,7 @@ class AlphaDynInst : public BaseDynInst FullCPU *cpu); /** BaseDynInst constructor given a static inst pointer. */ - AlphaDynInst(StaticInstPtr &_staticInst); + AlphaDynInst(StaticInstPtr &_staticInst); /** Executes the instruction.*/ Fault * execute() @@ -130,22 +127,22 @@ class AlphaDynInst : public BaseDynInst // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst *si, int idx) + uint64_t readIntReg(const StaticInst *si, int idx) { return this->cpu->readIntReg(_srcRegIdx[idx]); } - float readFloatRegSingle(const StaticInst *si, int idx) + float readFloatRegSingle(const StaticInst *si, int idx) { return this->cpu->readFloatRegSingle(_srcRegIdx[idx]); } - double readFloatRegDouble(const StaticInst *si, int idx) + double readFloatRegDouble(const StaticInst *si, int idx) { return this->cpu->readFloatRegDouble(_srcRegIdx[idx]); } - uint64_t readFloatRegInt(const StaticInst *si, int idx) + uint64_t readFloatRegInt(const StaticInst *si, int idx) { return this->cpu->readFloatRegInt(_srcRegIdx[idx]); } @@ -153,25 +150,25 @@ class AlphaDynInst : public BaseDynInst /** @todo: Make results into arrays so they can handle multiple dest * registers. */ - void setIntReg(const StaticInst *si, int idx, uint64_t val) + void setIntReg(const StaticInst *si, int idx, uint64_t val) { this->cpu->setIntReg(_destRegIdx[idx], val); this->instResult.integer = val; } - void setFloatRegSingle(const StaticInst *si, int idx, float val) + void setFloatRegSingle(const StaticInst *si, int idx, float val) { this->cpu->setFloatRegSingle(_destRegIdx[idx], val); this->instResult.fp = val; } - void setFloatRegDouble(const StaticInst *si, int idx, double val) + void setFloatRegDouble(const StaticInst *si, int idx, double val) { this->cpu->setFloatRegDouble(_destRegIdx[idx], val); this->instResult.dbl = val; } - void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) + void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) { this->cpu->setFloatRegInt(_destRegIdx[idx], val); this->instResult.integer = val; diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh index b20af48cd..9f9df3da1 100644 --- a/cpu/o3/alpha_dyn_inst_impl.hh +++ b/cpu/o3/alpha_dyn_inst_impl.hh @@ -50,7 +50,7 @@ AlphaDynInst::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC, } template -AlphaDynInst::AlphaDynInst(StaticInstPtr &_staticInst) +AlphaDynInst::AlphaDynInst(StaticInstPtr &_staticInst) : BaseDynInst(_staticInst) { // Make sure to have the renamed register entries set to the same diff --git a/cpu/o3/alpha_impl.hh b/cpu/o3/alpha_impl.hh index 6c1156041..5e39fcb37 100644 --- a/cpu/o3/alpha_impl.hh +++ b/cpu/o3/alpha_impl.hh @@ -51,11 +51,8 @@ class AlphaFullCPU; */ struct AlphaSimpleImpl { - /** The ISA to be used. */ - typedef AlphaISA ISA; - /** The type of MachInst. */ - typedef ISA::MachInst MachInst; + typedef TheISA::MachInst MachInst; /** The CPU policy to be used (ie fetch, decode, etc.). */ typedef SimpleCPUPolicy CPUPol; diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh index 0a77b83dc..c874f9e04 100644 --- a/cpu/o3/bpred_unit.hh +++ b/cpu/o3/bpred_unit.hh @@ -53,6 +53,8 @@ template class TwobitBPredUnit { + protected: + typedef TheISA::Addr Addr; public: typedef typename Impl::Params Params; typedef typename Impl::DynInstPtr DynInstPtr; diff --git a/cpu/o3/bpred_unit_impl.hh b/cpu/o3/bpred_unit_impl.hh index 9cb2e0490..8d16a0cdf 100644 --- a/cpu/o3/bpred_unit_impl.hh +++ b/cpu/o3/bpred_unit_impl.hh @@ -98,6 +98,8 @@ TwobitBPredUnit::predict(DynInstPtr &inst, Addr &PC) // Save off record of branch stuff so the RAS can be fixed // up once it's done. + using TheISA::MachInst; + bool pred_taken = false; Addr target; diff --git a/cpu/o3/btb.cc b/cpu/o3/btb.cc index 7671e61e2..2d39c3856 100644 --- a/cpu/o3/btb.cc +++ b/cpu/o3/btb.cc @@ -30,6 +30,8 @@ #include "base/trace.hh" #include "cpu/o3/btb.hh" +using namespace TheISA; + DefaultBTB::DefaultBTB(unsigned _numEntries, unsigned _tagBits, unsigned _instShiftAmt) diff --git a/cpu/o3/btb.hh b/cpu/o3/btb.hh index a4ddfecb4..f443ddbaf 100644 --- a/cpu/o3/btb.hh +++ b/cpu/o3/btb.hh @@ -30,10 +30,12 @@ #define __CPU_O3_CPU_BTB_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" class DefaultBTB { + protected: + typedef TheISA::Addr Addr; private: struct BTBEntry { diff --git a/cpu/o3/commit.hh b/cpu/o3/commit.hh index 6ddc8d6b9..580c1a316 100644 --- a/cpu/o3/commit.hh +++ b/cpu/o3/commit.hh @@ -52,7 +52,6 @@ class SimpleCommit { public: // Typedefs from the Impl. - typedef typename Impl::ISA ISA; typedef typename Impl::FullCPU FullCPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::Params Params; diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index adc7b6bbc..ffa157fbb 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -84,14 +84,14 @@ FullO3CPU::FullO3CPU(Params ¶ms) regFile(params.numPhysIntRegs, params.numPhysFloatRegs), - freeList(Impl::ISA::NumIntRegs, params.numPhysIntRegs, - Impl::ISA::NumFloatRegs, params.numPhysFloatRegs), + freeList(TheISA::NumIntRegs, params.numPhysIntRegs, + TheISA::NumFloatRegs, params.numPhysFloatRegs), - renameMap(Impl::ISA::NumIntRegs, params.numPhysIntRegs, - Impl::ISA::NumFloatRegs, params.numPhysFloatRegs, - Impl::ISA::NumMiscRegs, - Impl::ISA::ZeroReg, - Impl::ISA::ZeroReg + Impl::ISA::NumIntRegs), + renameMap(TheISA::NumIntRegs, params.numPhysIntRegs, + TheISA::NumFloatRegs, params.numPhysFloatRegs, + TheISA::NumMiscRegs, + TheISA::ZeroReg, + TheISA::ZeroReg + TheISA::NumIntRegs), rob(params.numROBEntries, params.squashWidth), @@ -254,13 +254,13 @@ FullO3CPU::init() ExecContext *src_xc = thread[0]; #endif // First loop through the integer registers. - for (int i = 0; i < Impl::ISA::NumIntRegs; ++i) + for (int i = 0; i < TheISA::NumIntRegs; ++i) { regFile.intRegFile[i] = src_xc->regs.intRegFile[i]; } // Then loop through the floating point registers. - for (int i = 0; i < Impl::ISA::NumFloatRegs; ++i) + for (int i = 0; i < TheISA::NumFloatRegs; ++i) { regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i]; regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i]; diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 75dca5056..321d61dce 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -78,7 +78,6 @@ class FullO3CPU : public BaseFullCPU { public: //Put typedefs from the Impl here. - typedef typename Impl::ISA ISA; typedef typename Impl::CPUPol CPUPolicy; typedef typename Impl::Params Params; typedef typename Impl::DynInstPtr DynInstPtr; @@ -153,11 +152,11 @@ class FullO3CPU : public BaseFullCPU /** Get instruction asid. */ int getInstAsid() - { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); } + { return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); } /** Get data asid. */ int getDataAsid() - { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); } + { return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); } #else bool validInstAddr(Addr addr) { return thread[0]->validInstAddr(addr); } diff --git a/cpu/o3/decode.hh b/cpu/o3/decode.hh index 42313d83a..bae9a7015 100644 --- a/cpu/o3/decode.hh +++ b/cpu/o3/decode.hh @@ -39,7 +39,6 @@ class SimpleDecode { private: // Typedefs from the Impl. - typedef typename Impl::ISA ISA; typedef typename Impl::FullCPU FullCPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::Params Params; @@ -51,7 +50,7 @@ class SimpleDecode typedef typename CPUPol::TimeStruct TimeStruct; // Typedefs from the ISA. - typedef typename ISA::Addr Addr; + typedef TheISA::Addr Addr; public: // The only time decode will become blocked is if dispatch becomes diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh index 5443d274e..e4d374c1d 100644 --- a/cpu/o3/fetch.hh +++ b/cpu/o3/fetch.hh @@ -49,7 +49,6 @@ class SimpleFetch { public: /** Typedefs from Impl. */ - typedef typename Impl::ISA ISA; typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInst DynInst; typedef typename Impl::DynInstPtr DynInstPtr; @@ -61,7 +60,8 @@ class SimpleFetch typedef typename CPUPol::TimeStruct TimeStruct; /** Typedefs from ISA. */ - typedef typename ISA::MachInst MachInst; + typedef TheISA::MachInst MachInst; + typedef TheISA::Addr Addr; public: enum Status { @@ -141,7 +141,7 @@ class SimpleFetch // We fold in the PISA 64- to 32-bit conversion here as well. Addr icacheBlockAlignPC(Addr addr) { - addr = ISA::realPCToFetchPC(addr); + addr = TheISA::realPCToFetchPC(addr); return (addr & ~(cacheBlkMask)); } diff --git a/cpu/o3/free_list.hh b/cpu/o3/free_list.hh index 733d142fc..0b85dba1e 100644 --- a/cpu/o3/free_list.hh +++ b/cpu/o3/free_list.hh @@ -32,7 +32,7 @@ #include #include -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "base/trace.hh" #include "base/traceflags.hh" #include "cpu/o3/comm.hh" diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh index af23c6f45..1e370d4e6 100644 --- a/cpu/o3/iew.hh +++ b/cpu/o3/iew.hh @@ -45,7 +45,6 @@ class SimpleIEW { private: //Typedefs from Impl - typedef typename Impl::ISA ISA; typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::FullCPU FullCPU; diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh index b8a2b4dc9..85217dd10 100644 --- a/cpu/o3/iew_impl.hh +++ b/cpu/o3/iew_impl.hh @@ -256,7 +256,7 @@ SimpleIEW::squashDueToBranch(DynInstPtr &inst) toCommit->branchMispredict = true; // Prediction was incorrect, so send back inverse. toCommit->branchTaken = inst->readNextPC() != - (inst->readPC() + sizeof(MachInst)); + (inst->readPC() + sizeof(TheISA::MachInst)); } template diff --git a/cpu/o3/ras.hh b/cpu/o3/ras.hh index bbc4162a6..fd7f5fe1c 100644 --- a/cpu/o3/ras.hh +++ b/cpu/o3/ras.hh @@ -30,10 +30,12 @@ #define __CPU_O3_CPU_RAS_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" class ReturnAddrStack { + protected: + typedef TheISA::Addr Addr; public: ReturnAddrStack(unsigned numEntries); diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 5aafd5495..655a3cad9 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -52,6 +52,11 @@ using namespace EV5; template class PhysRegFile { + protected: + typedef TheISA::Addr Addr; + typedef TheISA::IntReg IntReg; + typedef TheISA::FloatReg FloatReg; + typedef TheISA::MiscRegFile MiscRegFile; //Note that most of the definitions of the IntReg, FloatReg, etc. exist //within the Impl/ISA class and not within this PhysRegFile class. @@ -62,7 +67,6 @@ class PhysRegFile //Will make these registers public for now, but they probably should //be private eventually with some accessor functions. public: - typedef typename Impl::ISA ISA; typedef typename Impl::FullCPU FullCPU; PhysRegFile(unsigned _numPhysicalIntRegs, @@ -281,73 +285,73 @@ PhysRegFile::readIpr(int idx, Fault * &fault) uint64_t retval = 0; // return value, default 0 switch (idx) { - case ISA::IPR_PALtemp0: - case ISA::IPR_PALtemp1: - case ISA::IPR_PALtemp2: - case ISA::IPR_PALtemp3: - case ISA::IPR_PALtemp4: - case ISA::IPR_PALtemp5: - case ISA::IPR_PALtemp6: - case ISA::IPR_PALtemp7: - case ISA::IPR_PALtemp8: - case ISA::IPR_PALtemp9: - case ISA::IPR_PALtemp10: - case ISA::IPR_PALtemp11: - case ISA::IPR_PALtemp12: - case ISA::IPR_PALtemp13: - case ISA::IPR_PALtemp14: - case ISA::IPR_PALtemp15: - case ISA::IPR_PALtemp16: - case ISA::IPR_PALtemp17: - case ISA::IPR_PALtemp18: - case ISA::IPR_PALtemp19: - case ISA::IPR_PALtemp20: - case ISA::IPR_PALtemp21: - case ISA::IPR_PALtemp22: - case ISA::IPR_PALtemp23: - case ISA::IPR_PAL_BASE: - - case ISA::IPR_IVPTBR: - case ISA::IPR_DC_MODE: - case ISA::IPR_MAF_MODE: - case ISA::IPR_ISR: - case ISA::IPR_EXC_ADDR: - case ISA::IPR_IC_PERR_STAT: - case ISA::IPR_DC_PERR_STAT: - case ISA::IPR_MCSR: - case ISA::IPR_ASTRR: - case ISA::IPR_ASTER: - case ISA::IPR_SIRR: - case ISA::IPR_ICSR: - case ISA::IPR_ICM: - case ISA::IPR_DTB_CM: - case ISA::IPR_IPLR: - case ISA::IPR_INTID: - case ISA::IPR_PMCTR: + case TheISA::IPR_PALtemp0: + case TheISA::IPR_PALtemp1: + case TheISA::IPR_PALtemp2: + case TheISA::IPR_PALtemp3: + case TheISA::IPR_PALtemp4: + case TheISA::IPR_PALtemp5: + case TheISA::IPR_PALtemp6: + case TheISA::IPR_PALtemp7: + case TheISA::IPR_PALtemp8: + case TheISA::IPR_PALtemp9: + case TheISA::IPR_PALtemp10: + case TheISA::IPR_PALtemp11: + case TheISA::IPR_PALtemp12: + case TheISA::IPR_PALtemp13: + case TheISA::IPR_PALtemp14: + case TheISA::IPR_PALtemp15: + case TheISA::IPR_PALtemp16: + case TheISA::IPR_PALtemp17: + case TheISA::IPR_PALtemp18: + case TheISA::IPR_PALtemp19: + case TheISA::IPR_PALtemp20: + case TheISA::IPR_PALtemp21: + case TheISA::IPR_PALtemp22: + case TheISA::IPR_PALtemp23: + case TheISA::IPR_PAL_BASE: + + case TheISA::IPR_IVPTBR: + case TheISA::IPR_DC_MODE: + case TheISA::IPR_MAF_MODE: + case TheISA::IPR_ISR: + case TheISA::IPR_EXC_ADDR: + case TheISA::IPR_IC_PERR_STAT: + case TheISA::IPR_DC_PERR_STAT: + case TheISA::IPR_MCSR: + case TheISA::IPR_ASTRR: + case TheISA::IPR_ASTER: + case TheISA::IPR_SIRR: + case TheISA::IPR_ICSR: + case TheISA::IPR_ICM: + case TheISA::IPR_DTB_CM: + case TheISA::IPR_IPLR: + case TheISA::IPR_INTID: + case TheISA::IPR_PMCTR: // no side-effect retval = ipr[idx]; break; - case ISA::IPR_CC: + case TheISA::IPR_CC: retval |= ipr[idx] & ULL(0xffffffff00000000); retval |= curTick & ULL(0x00000000ffffffff); break; - case ISA::IPR_VA: + case TheISA::IPR_VA: retval = ipr[idx]; break; - case ISA::IPR_VA_FORM: - case ISA::IPR_MM_STAT: - case ISA::IPR_IFAULT_VA_FORM: - case ISA::IPR_EXC_MASK: - case ISA::IPR_EXC_SUM: + case TheISA::IPR_VA_FORM: + case TheISA::IPR_MM_STAT: + case TheISA::IPR_IFAULT_VA_FORM: + case TheISA::IPR_EXC_MASK: + case TheISA::IPR_EXC_SUM: retval = ipr[idx]; break; - case ISA::IPR_DTB_PTE: + case TheISA::IPR_DTB_PTE: { - typename ISA::PTE &pte = cpu->dtb->index(1); + TheISA::PTE &pte = cpu->dtb->index(1); retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; @@ -360,15 +364,15 @@ PhysRegFile::readIpr(int idx, Fault * &fault) break; // write only registers - case ISA::IPR_HWINT_CLR: - case ISA::IPR_SL_XMIT: - case ISA::IPR_DC_FLUSH: - case ISA::IPR_IC_FLUSH: - case ISA::IPR_ALT_MODE: - case ISA::IPR_DTB_IA: - case ISA::IPR_DTB_IAP: - case ISA::IPR_ITB_IA: - case ISA::IPR_ITB_IAP: + case TheISA::IPR_HWINT_CLR: + case TheISA::IPR_SL_XMIT: + case TheISA::IPR_DC_FLUSH: + case TheISA::IPR_IC_FLUSH: + case TheISA::IPR_ALT_MODE: + case TheISA::IPR_DTB_IA: + case TheISA::IPR_DTB_IAP: + case TheISA::IPR_ITB_IA: + case TheISA::IPR_ITB_IAP: fault = UnimplementedOpcodeFault; break; @@ -390,195 +394,195 @@ PhysRegFile::setIpr(int idx, uint64_t val) uint64_t old; switch (idx) { - case ISA::IPR_PALtemp0: - case ISA::IPR_PALtemp1: - case ISA::IPR_PALtemp2: - case ISA::IPR_PALtemp3: - case ISA::IPR_PALtemp4: - case ISA::IPR_PALtemp5: - case ISA::IPR_PALtemp6: - case ISA::IPR_PALtemp7: - case ISA::IPR_PALtemp8: - case ISA::IPR_PALtemp9: - case ISA::IPR_PALtemp10: - case ISA::IPR_PALtemp11: - case ISA::IPR_PALtemp12: - case ISA::IPR_PALtemp13: - case ISA::IPR_PALtemp14: - case ISA::IPR_PALtemp15: - case ISA::IPR_PALtemp16: - case ISA::IPR_PALtemp17: - case ISA::IPR_PALtemp18: - case ISA::IPR_PALtemp19: - case ISA::IPR_PALtemp20: - case ISA::IPR_PALtemp21: - case ISA::IPR_PALtemp22: - case ISA::IPR_PAL_BASE: - case ISA::IPR_IC_PERR_STAT: - case ISA::IPR_DC_PERR_STAT: - case ISA::IPR_PMCTR: + case TheISA::IPR_PALtemp0: + case TheISA::IPR_PALtemp1: + case TheISA::IPR_PALtemp2: + case TheISA::IPR_PALtemp3: + case TheISA::IPR_PALtemp4: + case TheISA::IPR_PALtemp5: + case TheISA::IPR_PALtemp6: + case TheISA::IPR_PALtemp7: + case TheISA::IPR_PALtemp8: + case TheISA::IPR_PALtemp9: + case TheISA::IPR_PALtemp10: + case TheISA::IPR_PALtemp11: + case TheISA::IPR_PALtemp12: + case TheISA::IPR_PALtemp13: + case TheISA::IPR_PALtemp14: + case TheISA::IPR_PALtemp15: + case TheISA::IPR_PALtemp16: + case TheISA::IPR_PALtemp17: + case TheISA::IPR_PALtemp18: + case TheISA::IPR_PALtemp19: + case TheISA::IPR_PALtemp20: + case TheISA::IPR_PALtemp21: + case TheISA::IPR_PALtemp22: + case TheISA::IPR_PAL_BASE: + case TheISA::IPR_IC_PERR_STAT: + case TheISA::IPR_DC_PERR_STAT: + case TheISA::IPR_PMCTR: // write entire quad w/ no side-effect ipr[idx] = val; break; - case ISA::IPR_CC_CTL: + case TheISA::IPR_CC_CTL: // This IPR resets the cycle counter. We assume this only // happens once... let's verify that. assert(ipr[idx] == 0); ipr[idx] = 1; break; - case ISA::IPR_CC: + case TheISA::IPR_CC: // This IPR only writes the upper 64 bits. It's ok to write // all 64 here since we mask out the lower 32 in rpcc (see // isa_desc). ipr[idx] = val; break; - case ISA::IPR_PALtemp23: + case TheISA::IPR_PALtemp23: // write entire quad w/ no side-effect old = ipr[idx]; ipr[idx] = val; break; - case ISA::IPR_DTB_PTE: + case TheISA::IPR_DTB_PTE: // write entire quad w/ no side-effect, tag is forthcoming ipr[idx] = val; break; - case ISA::IPR_EXC_ADDR: + case TheISA::IPR_EXC_ADDR: // second least significant bit in PC is always zero ipr[idx] = val & ~2; break; - case ISA::IPR_ASTRR: - case ISA::IPR_ASTER: + case TheISA::IPR_ASTRR: + case TheISA::IPR_ASTER: // only write least significant four bits - privilege mask ipr[idx] = val & 0xf; break; - case ISA::IPR_IPLR: + case TheISA::IPR_IPLR: // only write least significant five bits - interrupt level ipr[idx] = val & 0x1f; break; - case ISA::IPR_DTB_CM: + case TheISA::IPR_DTB_CM: - case ISA::IPR_ICM: + case TheISA::IPR_ICM: // only write two mode bits - processor mode ipr[idx] = val & 0x18; break; - case ISA::IPR_ALT_MODE: + case TheISA::IPR_ALT_MODE: // only write two mode bits - processor mode ipr[idx] = val & 0x18; break; - case ISA::IPR_MCSR: + case TheISA::IPR_MCSR: // more here after optimization... ipr[idx] = val; break; - case ISA::IPR_SIRR: + case TheISA::IPR_SIRR: // only write software interrupt mask ipr[idx] = val & 0x7fff0; break; - case ISA::IPR_ICSR: + case TheISA::IPR_ICSR: ipr[idx] = val & ULL(0xffffff0300); break; - case ISA::IPR_IVPTBR: - case ISA::IPR_MVPTBR: + case TheISA::IPR_IVPTBR: + case TheISA::IPR_MVPTBR: ipr[idx] = val & ULL(0xffffffffc0000000); break; - case ISA::IPR_DC_TEST_CTL: + case TheISA::IPR_DC_TEST_CTL: ipr[idx] = val & 0x1ffb; break; - case ISA::IPR_DC_MODE: - case ISA::IPR_MAF_MODE: + case TheISA::IPR_DC_MODE: + case TheISA::IPR_MAF_MODE: ipr[idx] = val & 0x3f; break; - case ISA::IPR_ITB_ASN: + case TheISA::IPR_ITB_ASN: ipr[idx] = val & 0x7f0; break; - case ISA::IPR_DTB_ASN: + case TheISA::IPR_DTB_ASN: ipr[idx] = val & ULL(0xfe00000000000000); break; - case ISA::IPR_EXC_SUM: - case ISA::IPR_EXC_MASK: + case TheISA::IPR_EXC_SUM: + case TheISA::IPR_EXC_MASK: // any write to this register clears it ipr[idx] = 0; break; - case ISA::IPR_INTID: - case ISA::IPR_SL_RCV: - case ISA::IPR_MM_STAT: - case ISA::IPR_ITB_PTE_TEMP: - case ISA::IPR_DTB_PTE_TEMP: + case TheISA::IPR_INTID: + case TheISA::IPR_SL_RCV: + case TheISA::IPR_MM_STAT: + case TheISA::IPR_ITB_PTE_TEMP: + case TheISA::IPR_DTB_PTE_TEMP: // read-only registers return UnimplementedOpcodeFault; - case ISA::IPR_HWINT_CLR: - case ISA::IPR_SL_XMIT: - case ISA::IPR_DC_FLUSH: - case ISA::IPR_IC_FLUSH: + case TheISA::IPR_HWINT_CLR: + case TheISA::IPR_SL_XMIT: + case TheISA::IPR_DC_FLUSH: + case TheISA::IPR_IC_FLUSH: // the following are write only ipr[idx] = val; break; - case ISA::IPR_DTB_IA: + case TheISA::IPR_DTB_IA: // really a control write ipr[idx] = 0; cpu->dtb->flushAll(); break; - case ISA::IPR_DTB_IAP: + case TheISA::IPR_DTB_IAP: // really a control write ipr[idx] = 0; cpu->dtb->flushProcesses(); break; - case ISA::IPR_DTB_IS: + case TheISA::IPR_DTB_IS: // really a control write ipr[idx] = val; - cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN])); + cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN])); break; - case ISA::IPR_DTB_TAG: { - struct ISA::PTE pte; + case TheISA::IPR_DTB_TAG: { + struct TheISA::PTE pte; // FIXME: granularity hints NYI... - if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0) + if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0) panic("PTE GH field != 0"); // write entire quad ipr[idx] = val; // construct PTE for new entry - pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]); - pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]); - pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]); - pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]); - pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]); - pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]); - pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]); + pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]); + pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]); + pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]); + pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]); + pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]); + pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]); + pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]); // insert new TAG/PTE value into data TLB cpu->dtb->insert(val, pte); } break; - case ISA::IPR_ITB_PTE: { - struct ISA::PTE pte; + case TheISA::IPR_ITB_PTE: { + struct TheISA::PTE pte; // FIXME: granularity hints NYI... if (ITB_PTE_GH(val) != 0) @@ -594,32 +598,32 @@ PhysRegFile::setIpr(int idx, uint64_t val) pte.fonr = ITB_PTE_FONR(val); pte.fonw = ITB_PTE_FONW(val); pte.asma = ITB_PTE_ASMA(val); - pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]); + pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]); // insert new TAG/PTE value into data TLB - cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte); + cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte); } break; - case ISA::IPR_ITB_IA: + case TheISA::IPR_ITB_IA: // really a control write ipr[idx] = 0; cpu->itb->flushAll(); break; - case ISA::IPR_ITB_IAP: + case TheISA::IPR_ITB_IAP: // really a control write ipr[idx] = 0; cpu->itb->flushProcesses(); break; - case ISA::IPR_ITB_IS: + case TheISA::IPR_ITB_IS: // really a control write ipr[idx] = val; - cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN])); + cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN])); break; default: diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh index a17ec7311..9781480b6 100644 --- a/cpu/o3/rename.hh +++ b/cpu/o3/rename.hh @@ -46,7 +46,6 @@ class SimpleRename { public: // Typedefs from the Impl. - typedef typename Impl::ISA ISA; typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::FullCPU FullCPU; @@ -62,7 +61,8 @@ class SimpleRename typedef typename CPUPol::RenameMap RenameMap; // Typedefs from the ISA. - typedef typename ISA::Addr Addr; + typedef TheISA::Addr Addr; + typedef TheISA::RegIndex RegIndex; public: // Rename will block if ROB becomes full or issue queue becomes full, diff --git a/cpu/o3/rename_map.hh b/cpu/o3/rename_map.hh index c44c7a1ea..57be4a64a 100644 --- a/cpu/o3/rename_map.hh +++ b/cpu/o3/rename_map.hh @@ -38,9 +38,13 @@ #include #include "cpu/o3/free_list.hh" +//For RegIndex +#include "arch/isa_traits.hh" class SimpleRenameMap { + protected: + typedef TheISA::RegIndex RegIndex; public: /** * Pair of a logical register and a physical register. Tells the diff --git a/cpu/o3/rob.hh b/cpu/o3/rob.hh index 29ec48007..1185564ad 100644 --- a/cpu/o3/rob.hh +++ b/cpu/o3/rob.hh @@ -47,6 +47,8 @@ template class ROB { + protected: + typedef TheISA::RegIndex RegIndex; public: //Typedefs from the Impl. typedef typename Impl::FullCPU FullCPU; diff --git a/cpu/o3/store_set.hh b/cpu/o3/store_set.hh index bcd590384..c67d30fcb 100644 --- a/cpu/o3/store_set.hh +++ b/cpu/o3/store_set.hh @@ -31,11 +31,13 @@ #include -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" class StoreSet { + protected: + typedef TheISA::Addr Addr; public: typedef unsigned SSID; diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh index 58ea1a7d9..6cfd24cfb 100644 --- a/cpu/o3/tournament_pred.hh +++ b/cpu/o3/tournament_pred.hh @@ -30,11 +30,13 @@ #define __CPU_O3_CPU_TOURNAMENT_PRED_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/o3/sat_counter.hh" class TournamentBP { + protected: + typedef TheISA::Addr Addr; public: /** * Default branch predictor constructor. -- cgit v1.2.3 From 3f7979c99d8dc4f434e3daa2e179616f1669e16e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 21 Feb 2006 03:38:21 -0500 Subject: Made Addr a global type --HG-- extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835 --- cpu/o3/2bit_local_pred.hh | 2 -- cpu/o3/alpha_cpu.hh | 1 - cpu/o3/alpha_dyn_inst.hh | 2 -- cpu/o3/bpred_unit.hh | 2 -- cpu/o3/btb.hh | 2 -- cpu/o3/decode.hh | 3 --- cpu/o3/fetch.hh | 1 - cpu/o3/ras.hh | 2 -- cpu/o3/regfile.hh | 1 - cpu/o3/rename.hh | 1 - cpu/o3/store_set.hh | 2 -- cpu/o3/tournament_pred.hh | 2 -- 12 files changed, 21 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh index 78efe1e43..97433e542 100644 --- a/cpu/o3/2bit_local_pred.hh +++ b/cpu/o3/2bit_local_pred.hh @@ -35,8 +35,6 @@ class DefaultBP { - protected: - typedef TheISA::Addr Addr; public: /** * Default branch predictor constructor. diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index bf3556b8e..2be70f5c2 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -40,7 +40,6 @@ template class AlphaFullCPU : public FullO3CPU { protected: - typedef AlphaISA::Addr Addr; typedef TheISA::IntReg IntReg; public: typedef typename Impl::Params Params; diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index 22be2aae5..b113d9487 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -50,8 +50,6 @@ class AlphaDynInst : public BaseDynInst /** Binary machine instruction type. */ typedef TheISA::MachInst MachInst; - /** Memory address type. */ - typedef TheISA::Addr Addr; /** Logical register index type. */ typedef TheISA::RegIndex RegIndex; /** Integer register index type. */ diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh index c874f9e04..0a77b83dc 100644 --- a/cpu/o3/bpred_unit.hh +++ b/cpu/o3/bpred_unit.hh @@ -53,8 +53,6 @@ template class TwobitBPredUnit { - protected: - typedef TheISA::Addr Addr; public: typedef typename Impl::Params Params; typedef typename Impl::DynInstPtr DynInstPtr; diff --git a/cpu/o3/btb.hh b/cpu/o3/btb.hh index f443ddbaf..77bdc32ea 100644 --- a/cpu/o3/btb.hh +++ b/cpu/o3/btb.hh @@ -34,8 +34,6 @@ class DefaultBTB { - protected: - typedef TheISA::Addr Addr; private: struct BTBEntry { diff --git a/cpu/o3/decode.hh b/cpu/o3/decode.hh index bae9a7015..5b9a0f822 100644 --- a/cpu/o3/decode.hh +++ b/cpu/o3/decode.hh @@ -49,9 +49,6 @@ class SimpleDecode typedef typename CPUPol::DecodeStruct DecodeStruct; typedef typename CPUPol::TimeStruct TimeStruct; - // Typedefs from the ISA. - typedef TheISA::Addr Addr; - public: // The only time decode will become blocked is if dispatch becomes // blocked, which means IQ or ROB is probably full. diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh index e4d374c1d..82a6cd818 100644 --- a/cpu/o3/fetch.hh +++ b/cpu/o3/fetch.hh @@ -61,7 +61,6 @@ class SimpleFetch /** Typedefs from ISA. */ typedef TheISA::MachInst MachInst; - typedef TheISA::Addr Addr; public: enum Status { diff --git a/cpu/o3/ras.hh b/cpu/o3/ras.hh index fd7f5fe1c..46d98181e 100644 --- a/cpu/o3/ras.hh +++ b/cpu/o3/ras.hh @@ -34,8 +34,6 @@ class ReturnAddrStack { - protected: - typedef TheISA::Addr Addr; public: ReturnAddrStack(unsigned numEntries); diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 655a3cad9..021f9b0b6 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -53,7 +53,6 @@ template class PhysRegFile { protected: - typedef TheISA::Addr Addr; typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::MiscRegFile MiscRegFile; diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh index 9781480b6..07b442964 100644 --- a/cpu/o3/rename.hh +++ b/cpu/o3/rename.hh @@ -61,7 +61,6 @@ class SimpleRename typedef typename CPUPol::RenameMap RenameMap; // Typedefs from the ISA. - typedef TheISA::Addr Addr; typedef TheISA::RegIndex RegIndex; public: diff --git a/cpu/o3/store_set.hh b/cpu/o3/store_set.hh index c67d30fcb..5a885d838 100644 --- a/cpu/o3/store_set.hh +++ b/cpu/o3/store_set.hh @@ -36,8 +36,6 @@ class StoreSet { - protected: - typedef TheISA::Addr Addr; public: typedef unsigned SSID; diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh index 6cfd24cfb..cb93c2f67 100644 --- a/cpu/o3/tournament_pred.hh +++ b/cpu/o3/tournament_pred.hh @@ -35,8 +35,6 @@ class TournamentBP { - protected: - typedef TheISA::Addr Addr; public: /** * Default branch predictor constructor. -- cgit v1.2.3 From 8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 21 Feb 2006 20:10:40 -0500 Subject: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. --HG-- extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb --- cpu/o3/alpha_cpu.hh | 34 +++++++++++++++++----------------- cpu/o3/alpha_cpu_impl.hh | 8 ++++---- cpu/o3/alpha_dyn_inst.hh | 14 +++++++------- cpu/o3/alpha_dyn_inst_impl.hh | 8 ++++---- cpu/o3/commit_impl.hh | 2 +- cpu/o3/fetch.hh | 2 +- cpu/o3/fetch_impl.hh | 6 +++--- cpu/o3/regfile.hh | 8 ++++---- 8 files changed, 41 insertions(+), 41 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index 2be70f5c2..b35bcf9e3 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -63,23 +63,23 @@ class AlphaFullCPU : public FullO3CPU // void clear_interrupt(int int_num, int index); // void clear_interrupts(); - Fault * translateInstReq(MemReqPtr &req) + Fault translateInstReq(MemReqPtr &req) { return itb->translate(req); } - Fault * translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(MemReqPtr &req) { return dtb->translate(req, false); } - Fault * translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(MemReqPtr &req) { return dtb->translate(req, true); } #else - Fault * dummyTranslation(MemReqPtr &req) + Fault dummyTranslation(MemReqPtr &req) { #if 0 assert((req->vaddr >> 48 & 0xffff) == 0); @@ -91,17 +91,17 @@ class AlphaFullCPU : public FullO3CPU return NoFault; } - Fault * translateInstReq(MemReqPtr &req) + Fault translateInstReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault * translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault * translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(MemReqPtr &req) { return dummyTranslation(req); } @@ -136,16 +136,16 @@ class AlphaFullCPU : public FullO3CPU // look like. #if FULL_SYSTEM uint64_t *getIpr(); - uint64_t readIpr(int idx, Fault * &fault); - Fault * setIpr(int idx, uint64_t val); + uint64_t readIpr(int idx, Fault &fault); + Fault setIpr(int idx, uint64_t val); int readIntrFlag(); void setIntrFlag(int val); - Fault * hwrei(); + Fault hwrei(); bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); } bool inPalMode(uint64_t PC) { return AlphaISA::PcPAL(PC); } - void trap(Fault * fault); + void trap(Fault fault); bool simPalCheck(int palFunc); void processInterrupts(); @@ -198,7 +198,7 @@ class AlphaFullCPU : public FullO3CPU bool palShadowEnabled; // Not sure this is used anywhere. - void intr_post(RegFile *regs, Fault * fault, Addr pc); + void intr_post(RegFile *regs, Fault fault, Addr pc); // Actually used within exec files. Implement properly. void swapPALShadow(bool use_shadow); // Called by CPU constructor. Can implement as I please. @@ -211,7 +211,7 @@ class AlphaFullCPU : public FullO3CPU template - Fault * read(MemReqPtr &req, T &data) + Fault read(MemReqPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) if (req->flags & LOCKED) { @@ -221,20 +221,20 @@ class AlphaFullCPU : public FullO3CPU } #endif - Fault * error; + Fault error; error = this->mem->read(req, data); data = gtoh(data); return error; } template - Fault * read(MemReqPtr &req, T &data, int load_idx) + Fault read(MemReqPtr &req, T &data, int load_idx) { return this->iew.ldstQueue.read(req, data, load_idx); } template - Fault * write(MemReqPtr &req, T &data) + Fault write(MemReqPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) @@ -284,7 +284,7 @@ class AlphaFullCPU : public FullO3CPU } template - Fault * write(MemReqPtr &req, T &data, int store_idx) + Fault write(MemReqPtr &req, T &data, int store_idx) { return this->iew.ldstQueue.write(req, data, store_idx); } diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 6736cf9bc..7ec1ba663 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -246,13 +246,13 @@ AlphaFullCPU::getIpr() template uint64_t -AlphaFullCPU::readIpr(int idx, Fault * &fault) +AlphaFullCPU::readIpr(int idx, Fault &fault) { return this->regFile.readIpr(idx, fault); } template -Fault * +Fault AlphaFullCPU::setIpr(int idx, uint64_t val) { return this->regFile.setIpr(idx, val); @@ -274,7 +274,7 @@ AlphaFullCPU::setIntrFlag(int val) // Can force commit stage to squash and stuff. template -Fault * +Fault AlphaFullCPU::hwrei() { uint64_t *ipr = getIpr(); @@ -323,7 +323,7 @@ AlphaFullCPU::simPalCheck(int palFunc) // stage. template void -AlphaFullCPU::trap(Fault * fault) +AlphaFullCPU::trap(Fault fault) { // Keep in mind that a trap may be initiated by fetch if there's a TLB // miss diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index b113d9487..f282c287c 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -69,7 +69,7 @@ class AlphaDynInst : public BaseDynInst AlphaDynInst(StaticInstPtr &_staticInst); /** Executes the instruction.*/ - Fault * execute() + Fault execute() { return this->fault = this->staticInst->execute(this, this->traceData); } @@ -82,13 +82,13 @@ class AlphaDynInst : public BaseDynInst void setFpcr(uint64_t val); #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault * &fault); - Fault * setIpr(int idx, uint64_t val); - Fault * hwrei(); + uint64_t readIpr(int idx, Fault &fault); + Fault setIpr(int idx, uint64_t val); + Fault hwrei(); int readIntrFlag(); void setIntrFlag(int val); bool inPalMode(); - void trap(Fault * fault); + void trap(Fault fault); bool simPalCheck(int palFunc); #else void syscall(); @@ -215,12 +215,12 @@ class AlphaDynInst : public BaseDynInst } public: - Fault * calcEA() + Fault calcEA() { return this->staticInst->eaCompInst()->execute(this, this->traceData); } - Fault * memAccess() + Fault memAccess() { return this->staticInst->memAccInst()->execute(this, this->traceData); } diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh index 9f9df3da1..eebe7675a 100644 --- a/cpu/o3/alpha_dyn_inst_impl.hh +++ b/cpu/o3/alpha_dyn_inst_impl.hh @@ -98,20 +98,20 @@ AlphaDynInst::setFpcr(uint64_t val) #if FULL_SYSTEM template uint64_t -AlphaDynInst::readIpr(int idx, Fault * &fault) +AlphaDynInst::readIpr(int idx, Fault &fault) { return this->cpu->readIpr(idx, fault); } template -Fault * +Fault AlphaDynInst::setIpr(int idx, uint64_t val) { return this->cpu->setIpr(idx, val); } template -Fault * +Fault AlphaDynInst::hwrei() { return this->cpu->hwrei(); @@ -140,7 +140,7 @@ AlphaDynInst::inPalMode() template void -AlphaDynInst::trap(Fault * fault) +AlphaDynInst::trap(Fault fault) { this->cpu->trap(fault); } diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh index 47b4dfd00..e289bc0c0 100644 --- a/cpu/o3/commit_impl.hh +++ b/cpu/o3/commit_impl.hh @@ -393,7 +393,7 @@ SimpleCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) } // Check if the instruction caused a fault. If so, trap. - Fault * inst_fault = head_inst->getFault(); + Fault inst_fault = head_inst->getFault(); if (inst_fault != NoFault) { if (!head_inst->isNop()) { diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh index 82a6cd818..cc64800d9 100644 --- a/cpu/o3/fetch.hh +++ b/cpu/o3/fetch.hh @@ -122,7 +122,7 @@ class SimpleFetch * @param fetch_PC The PC address that is being fetched from. * @return Any fault that occured. */ - Fault * fetchCacheLine(Addr fetch_PC); + Fault fetchCacheLine(Addr fetch_PC); inline void doSquash(const Addr &new_PC); diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh index e8d333ed4..8029fc732 100644 --- a/cpu/o3/fetch_impl.hh +++ b/cpu/o3/fetch_impl.hh @@ -221,7 +221,7 @@ SimpleFetch::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC) } template -Fault * +Fault SimpleFetch::fetchCacheLine(Addr fetch_PC) { // Check if the instruction exists within the cache. @@ -236,7 +236,7 @@ SimpleFetch::fetchCacheLine(Addr fetch_PC) unsigned flags = 0; #endif // FULL_SYSTEM - Fault * fault = NoFault; + Fault fault = NoFault; // Align the fetch PC so it's at the start of a cache block. fetch_PC = icacheBlockAlignPC(fetch_PC); @@ -468,7 +468,7 @@ SimpleFetch::fetch() Addr fetch_PC = cpu->readPC(); // Fault code for memory access. - Fault * fault = NoFault; + Fault fault = NoFault; // If returning from the delay of a cache miss, then update the status // to running, otherwise do the cache access. Possibly move this up diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 021f9b0b6..ee7b8858e 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -215,8 +215,8 @@ class PhysRegFile } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault * &fault); - Fault * setIpr(int idx, uint64_t val); + uint64_t readIpr(int idx, Fault &fault); + Fault setIpr(int idx, uint64_t val); InternalProcReg *getIpr() { return ipr; } int readIntrFlag() { return intrflag; } void setIntrFlag(int val) { intrflag = val; } @@ -279,7 +279,7 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs, //the DynInst level. template uint64_t -PhysRegFile::readIpr(int idx, Fault * &fault) +PhysRegFile::readIpr(int idx, Fault &fault) { uint64_t retval = 0; // return value, default 0 @@ -387,7 +387,7 @@ PhysRegFile::readIpr(int idx, Fault * &fault) extern int break_ipl; template -Fault * +Fault PhysRegFile::setIpr(int idx, uint64_t val) { uint64_t old; -- cgit v1.2.3 From 1166d4f0bfe67a9dc178be3454b4f0eac38663ad Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 23 Feb 2006 14:50:16 -0500 Subject: Get rid of the xc from the alphaAccess/alphaConsole backdoor device. Now allocate an array of stacks indexed by cpu number which specify cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for their stacks before continuing. This change *REQUIRES* a the new console code to operate correctly. arch/alpha/ev5.cc: Add cpuId to initCPU/initIPR functions cpu/o3/cpu.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Move the cpu initilization into an init() function since it now needs the CPU id which isn't known at construction dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: instead of the bootstrap variables, add space for 64 cpu stacks in the alpha access structure. sim/system.cc: start all cpus immediately rather than just the first one --HG-- extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b --- cpu/o3/cpu.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index adc7b6bbc..6ea0ed7c7 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -137,8 +137,6 @@ FullO3CPU::FullO3CPU(Params ¶ms) system->execContexts[i] = new ExecContext(this, i, system, itb, dtb, mem); - // initialize CPU, including PC - TheISA::initCPU(&system->execContexts[i]->regs); execContexts.push_back(system->execContexts[i]); #else if (i < params.workload.size()) { @@ -250,6 +248,7 @@ FullO3CPU::init() // that it can start properly. #if FULL_SYSTEM ExecContext *src_xc = system->execContexts[0]; + TheISA::initCPU(&src_xc->regs, src_xc->cpu_id); #else ExecContext *src_xc = thread[0]; #endif -- cgit v1.2.3 From 08637efadc40a1003d68bba91dedb007fe10798c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 24 Feb 2006 01:51:45 -0500 Subject: Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type. arch/alpha/alpha_memory.cc: arch/alpha/isa/decoder.isa: Added news where faults are created. arch/alpha/ev5.cc: Changed places where a fault was compared to a fault type to use isA rather than == arch/alpha/faults.cc: arch/alpha/faults.hh: Changed Fault to be a RefCountingPtr arch/alpha/isa/fp.isa: Added a new where a FloatEnableFault was created. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: Added a new where an UnimplementedFault is created. base/refcnt.hh: Added include of stddef.h for the NULL macro cpu/base_dyn_inst.cc: Added a new where an UnimplementedOpcodeFault is created. cpu/o3/alpha_cpu_impl.hh: Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name() cpu/o3/regfile.hh: Added new where UnimplementedOpcodeFaults are created. cpu/simple/cpu.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created. dev/alpha_console.cc: Added news where MachineCheckFaults are created. dev/pcidev.hh: Added news where MachineCheckFaults are generated. dev/sinic.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables. kern/kernel_stats.cc: Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future. kern/kernel_stats.hh: Commented out the declaration of _fault. when fault() is called, the fault increments its own stat. sim/faults.cc: sim/faults.hh: Changed Fault from a FaultBase * to a RefCountingPtr. --HG-- extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d --- cpu/o3/alpha_cpu_impl.hh | 14 +++++++------- cpu/o3/regfile.hh | 8 ++++---- 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 7ec1ba663..c0ec1fb33 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -280,7 +280,7 @@ AlphaFullCPU::hwrei() uint64_t *ipr = getIpr(); if (!inPalMode()) - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); @@ -329,21 +329,21 @@ AlphaFullCPU::trap(Fault fault) // miss uint64_t PC = this->commit.readCommitPC(); - DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name"); - this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name")); + DPRINTF(Fault, "Fault %s\n", fault->name()); + this->recordEvent(csprintf("Fault %s", fault->name())); -// kernelStats.fault(fault); + //kernelStats.fault(fault); - if (fault == ArithmeticFault) + if (fault->isA()) panic("Arithmetic traps are unimplemented!"); AlphaISA::InternalProcReg *ipr = getIpr(); // exception restart address - Get the commit PC - if (fault != InterruptFault || !inPalMode(PC)) + if (!fault->isA() || !inPalMode(PC)) ipr[AlphaISA::IPR_EXC_ADDR] = PC; - if (fault == PalFault || fault == ArithmeticFault /* || + if (fault->isA() || fault->isA() /* || fault == InterruptFault && !PC_PAL(regs.pc) */) { // traps... skip faulting instruction ipr[AlphaISA::IPR_EXC_ADDR] += 4; diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index ee7b8858e..7e36a6ead 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -372,12 +372,12 @@ PhysRegFile::readIpr(int idx, Fault &fault) case TheISA::IPR_DTB_IAP: case TheISA::IPR_ITB_IA: case TheISA::IPR_ITB_IAP: - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; default: // invalid IPR - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; } @@ -525,7 +525,7 @@ PhysRegFile::setIpr(int idx, uint64_t val) case TheISA::IPR_ITB_PTE_TEMP: case TheISA::IPR_DTB_PTE_TEMP: // read-only registers - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; case TheISA::IPR_HWINT_CLR: case TheISA::IPR_SL_XMIT: @@ -627,7 +627,7 @@ PhysRegFile::setIpr(int idx, uint64_t val) default: // invalid IPR - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } // no error... -- cgit v1.2.3 From 802fd04f640b34d713f7ef75142e51d3d82559b9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 24 Feb 2006 03:51:21 -0500 Subject: Removed a stray ::. --HG-- extra : convert_revision : f6114b78e30e8cba5af6276042b0f043d8773739 --- cpu/o3/alpha_cpu.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index b35bcf9e3..ea0aae41f 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -280,7 +280,7 @@ class AlphaFullCPU : public FullO3CPU #endif - return this->mem->write(req, (T)::htog(data)); + return this->mem->write(req, (T)htog(data)); } template -- cgit v1.2.3 From 4b256577e01111e676f021c67478afec2289e175 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 01:32:49 -0500 Subject: Where architecture independent sources included arch/alpha/xxx.hh, they were changed to include targetarch/xxx.hh cpu/base_dyn_inst.cc: cpu/o3/bpred_unit.hh: cpu/o3/comm.hh: cpu/o3/cpu.hh: cpu/o3/regfile.hh: cpu/ozone/cpu_impl.hh: cpu/ozone/ea_list.cc: cpu/ozone/ea_list.hh: kern/kernel_stats.cc: Changed arch/alpha to targetarch sim/process.cc: Changed arch/alpha to targetarch, and removed gaurding ifdef --HG-- extra : convert_revision : 3c29e6baeb1cd900f7b5e11144a5d547a6c7c5ab --- cpu/o3/bpred_unit.hh | 2 +- cpu/o3/comm.hh | 2 +- cpu/o3/cpu.hh | 2 +- cpu/o3/regfile.hh | 6 +++--- 4 files changed, 6 insertions(+), 6 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh index 0a77b83dc..786ed861d 100644 --- a/cpu/o3/bpred_unit.hh +++ b/cpu/o3/bpred_unit.hh @@ -30,7 +30,7 @@ #define __BPRED_UNIT_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "targetarch/isa_traits.hh" #include "base/statistics.hh" #include "cpu/inst_seq.hh" diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh index e4de1d304..76ff4d689 100644 --- a/cpu/o3/comm.hh +++ b/cpu/o3/comm.hh @@ -31,7 +31,7 @@ #include -#include "arch/alpha/isa_traits.hh" +#include "targetarch/isa_traits.hh" #include "cpu/inst_seq.hh" #include "sim/host.hh" diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 321d61dce..f9e449548 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -50,7 +50,7 @@ #include "sim/process.hh" #if FULL_SYSTEM -#include "arch/alpha/ev5.hh" +#include "targetarch/ev5.hh" using namespace EV5; #endif diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 7e36a6ead..85df06b76 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -31,14 +31,14 @@ // @todo: Destructor -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/faults.hh" +#include "targetarch/isa_traits.hh" +#include "targetarch/faults.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/o3/comm.hh" #if FULL_SYSTEM -#include "arch/alpha/ev5.hh" +#include "targetarch/ev5.hh" #include "kern/kernel_stats.hh" using namespace EV5; -- cgit v1.2.3 From 1a0b326f5d4fafaef206a97ddd02598e120aebb9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 01:38:47 -0500 Subject: Changed targetarch to arch for isa_traits.hh include --HG-- extra : convert_revision : e7ae43d812140ec99b782394e54903153f8d0476 --- cpu/o3/bpred_unit.hh | 2 +- cpu/o3/comm.hh | 2 +- cpu/o3/regfile.hh | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh index 786ed861d..2725684f7 100644 --- a/cpu/o3/bpred_unit.hh +++ b/cpu/o3/bpred_unit.hh @@ -30,7 +30,7 @@ #define __BPRED_UNIT_HH__ // For Addr type. -#include "targetarch/isa_traits.hh" +#include "arch/isa_traits.hh" #include "base/statistics.hh" #include "cpu/inst_seq.hh" diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh index 76ff4d689..c74c77ddf 100644 --- a/cpu/o3/comm.hh +++ b/cpu/o3/comm.hh @@ -31,7 +31,7 @@ #include -#include "targetarch/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" #include "sim/host.hh" diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 85df06b76..9009db919 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -31,7 +31,7 @@ // @todo: Destructor -#include "targetarch/isa_traits.hh" +#include "arch/isa_traits.hh" #include "targetarch/faults.hh" #include "base/trace.hh" #include "config/full_system.hh" -- cgit v1.2.3 From c5dcd152f264a837f50d39f98d0f4f81478e3553 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 05:35:43 -0500 Subject: Changed targetarch to just arch. SConscript: Changed all of the "targetarch" files to be "arch" files arch/SConscript: Added all of the remaining targetarch files to isa_switch_hdrs --HG-- extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480 --- cpu/o3/alpha_cpu_builder.cc | 4 ++-- cpu/o3/cpu.hh | 2 +- cpu/o3/regfile.hh | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc index 3547fb1b5..0f6d0d35c 100644 --- a/cpu/o3/alpha_cpu_builder.cc +++ b/cpu/o3/alpha_cpu_builder.cc @@ -50,8 +50,8 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" -#include "targetarch/vtophys.hh" +#include "arch/alpha_memory.hh" +#include "arch/vtophys.hh" #else // !FULL_SYSTEM #include "mem/functional/functional.hh" #endif // FULL_SYSTEM diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index f9e449548..802860ab5 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -50,7 +50,7 @@ #include "sim/process.hh" #if FULL_SYSTEM -#include "targetarch/ev5.hh" +#include "arch/ev5.hh" using namespace EV5; #endif diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 9009db919..3bf96a37b 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -32,13 +32,13 @@ // @todo: Destructor #include "arch/isa_traits.hh" -#include "targetarch/faults.hh" +#include "arch/faults.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/o3/comm.hh" #if FULL_SYSTEM -#include "targetarch/ev5.hh" +#include "arch/ev5.hh" #include "kern/kernel_stats.hh" using namespace EV5; -- cgit v1.2.3 From f1ef4a8f06184df55e26268381cb4f8f56b77a50 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 06:05:10 -0500 Subject: Renamed arch files to remove alpha prefix, and changed alpha_memory.hh and cc to a more accurate tlb.hh and cc --HG-- rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/tlb.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh extra : convert_revision : 9fe6863cc37347d2a6bd716c529b0a4a50b36ea7 --- cpu/o3/alpha_cpu_builder.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc index 0f6d0d35c..95d2f8f37 100644 --- a/cpu/o3/alpha_cpu_builder.cc +++ b/cpu/o3/alpha_cpu_builder.cc @@ -50,7 +50,7 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "arch/alpha_memory.hh" +#include "arch/tlb.hh" #include "arch/vtophys.hh" #else // !FULL_SYSTEM #include "mem/functional/functional.hh" -- cgit v1.2.3 From 70b35bab5778799805fe9b6040b23eb1885dbfc3 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 27 Feb 2006 11:44:35 -0500 Subject: Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs. They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76 --- cpu/o3/alpha_cpu.hh | 50 +++--- cpu/o3/alpha_cpu_impl.hh | 46 ++--- cpu/o3/alpha_dyn_inst.hh | 34 +++- cpu/o3/alpha_dyn_inst_impl.hh | 42 ----- cpu/o3/cpu.cc | 4 +- cpu/o3/cpu.hh | 4 +- cpu/o3/regfile.hh | 391 ++---------------------------------------- 7 files changed, 77 insertions(+), 494 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index b35bcf9e3..47ea532a6 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -41,6 +41,8 @@ class AlphaFullCPU : public FullO3CPU { protected: typedef TheISA::IntReg IntReg; + typedef TheISA::MiscReg MiscReg; + public: typedef typename Impl::Params Params; @@ -111,33 +113,24 @@ class AlphaFullCPU : public FullO3CPU // Later on may want to remove this misc stuff from the regfile and // have it handled at this level. Might prove to be an issue when // trying to rename source/destination registers... - uint64_t readUniq() - { - return this->regFile.readUniq(); - } - - void setUniq(uint64_t val) + MiscReg readMiscReg(int misc_reg) { - this->regFile.setUniq(val); + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return 0; } - uint64_t readFpcr() + Fault setMiscReg(int misc_reg, const MiscReg &val) { - return this->regFile.readFpcr(); - } - - void setFpcr(uint64_t val) - { - this->regFile.setFpcr(val); + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return NoFault; } // Most of the full system code and syscall emulation is not yet // implemented. These functions do show what the final interface will // look like. #if FULL_SYSTEM - uint64_t *getIpr(); - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); int readIntrFlag(); void setIntrFlag(int val); Fault hwrei(); @@ -216,8 +209,8 @@ class AlphaFullCPU : public FullO3CPU #if FULL_SYSTEM && defined(TARGET_ALPHA) if (req->flags & LOCKED) { MiscRegFile *cregs = &req->xc->regs.miscRegs; - cregs->lock_addr = req->paddr; - cregs->lock_flag = true; + cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr); + cregs->setReg(TheISA::Lock_Flag_DepTag, true); } #endif @@ -242,22 +235,24 @@ class AlphaFullCPU : public FullO3CPU // If this is a store conditional, act appropriately if (req->flags & LOCKED) { - cregs = &this->xc->regs.miscRegs; + cregs = &req->xc->regs.miscRegs; if (req->flags & UNCACHEABLE) { // Don't update result register (see stq_c in isa_desc) req->result = 2; req->xc->storeCondFailures = 0;//Needed? [RGD] } else { - req->result = cregs->lock_flag; - if (!cregs->lock_flag || - ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { - cregs->lock_flag = false; + bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag); + Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag); + req->result = lock_flag; + if (!lock_flag || + ((lock_addr & ~0xf) != (req->paddr & ~0xf))) { + cregs->setReg(TheISA::Lock_Flag_DepTag, false); if (((++req->xc->storeCondFailures) % 100000) == 0) { std::cerr << "Warning: " << req->xc->storeCondFailures << " consecutive store conditional failures " - << "on cpu " << this->cpu_id + << "on cpu " << req->xc->cpu_id << std::endl; } return NoFault; @@ -273,8 +268,9 @@ class AlphaFullCPU : public FullO3CPU // through. for (int i = 0; i < this->system->execContexts.size(); i++){ cregs = &this->system->execContexts[i]->regs.miscRegs; - if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { - cregs->lock_flag = false; + if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) == + (req->paddr & ~0xf)) { + cregs->setReg(TheISA::Lock_Flag_DepTag, false); } } diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 7ec1ba663..bd4e34914 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -179,12 +179,12 @@ AlphaFullCPU::copyToXC() this->xc->regs.floatRegFile.q[i] = this->regFile.readFloatRegInt(renamed_reg); } - +/* this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr; this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq; this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag; this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr; - +*/ this->xc->regs.pc = this->rob.readHeadPC(); this->xc->regs.npc = this->xc->regs.pc+4; @@ -221,13 +221,13 @@ AlphaFullCPU::copyFromXC() this->regFile.setFloatRegInt(renamed_reg, this->xc->regs.floatRegFile.q[i]); } - + /* // Then loop through the misc registers. this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr; this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq; this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag; this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr; - + */ // Then finally set the PC and the next PC. // regFile.pc = xc->regs.pc; // regFile.npc = xc->regs.npc; @@ -237,27 +237,6 @@ AlphaFullCPU::copyFromXC() #if FULL_SYSTEM -template -uint64_t * -AlphaFullCPU::getIpr() -{ - return this->regFile.getIpr(); -} - -template -uint64_t -AlphaFullCPU::readIpr(int idx, Fault &fault) -{ - return this->regFile.readIpr(idx, fault); -} - -template -Fault -AlphaFullCPU::setIpr(int idx, uint64_t val) -{ - return this->regFile.setIpr(idx, val); -} - template int AlphaFullCPU::readIntrFlag() @@ -277,16 +256,14 @@ template Fault AlphaFullCPU::hwrei() { - uint64_t *ipr = getIpr(); - if (!inPalMode()) return UnimplementedOpcodeFault; - this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); + this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR)); // kernelStats.hwrei(); - if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0) + if ((this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0) // AlphaISA::swap_palshadow(®s, false); this->checkInterrupts = true; @@ -337,22 +314,23 @@ AlphaFullCPU::trap(Fault fault) if (fault == ArithmeticFault) panic("Arithmetic traps are unimplemented!"); - AlphaISA::InternalProcReg *ipr = getIpr(); - // exception restart address - Get the commit PC if (fault != InterruptFault || !inPalMode(PC)) - ipr[AlphaISA::IPR_EXC_ADDR] = PC; + this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC); if (fault == PalFault || fault == ArithmeticFault /* || fault == InterruptFault && !PC_PAL(regs.pc) */) { // traps... skip faulting instruction - ipr[AlphaISA::IPR_EXC_ADDR] += 4; + AlphaISA::MiscReg ipr_exc_addr = + this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR); + this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, + ipr_exc_addr + 4); } if (!inPalMode(PC)) swapPALShadow(true); - this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] + + this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) + AlphaISA::fault_addr(fault) ); this->regFile.setNextPC(PC + sizeof(MachInst)); } diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index f282c287c..e7f7d3a57 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -54,6 +54,8 @@ class AlphaDynInst : public BaseDynInst typedef TheISA::RegIndex RegIndex; /** Integer register index type. */ typedef TheISA::IntReg IntReg; + /** Misc register index type. */ + typedef TheISA::MiscReg MiscReg; enum { MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs @@ -75,15 +77,35 @@ class AlphaDynInst : public BaseDynInst } public: - uint64_t readUniq(); - void setUniq(uint64_t val); + MiscReg readMiscReg(int misc_reg) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return 0; + } + + MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return 0; + } - uint64_t readFpcr(); - void setFpcr(uint64_t val); + Fault setMiscReg(int misc_reg, const MiscReg &val) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return NoFault; + } + + Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return NoFault; + } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); Fault hwrei(); int readIntrFlag(); void setIntrFlag(int val); diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh index eebe7675a..96b7d3430 100644 --- a/cpu/o3/alpha_dyn_inst_impl.hh +++ b/cpu/o3/alpha_dyn_inst_impl.hh @@ -67,49 +67,7 @@ AlphaDynInst::AlphaDynInst(StaticInstPtr &_staticInst) } } -template -uint64_t -AlphaDynInst::readUniq() -{ - return this->cpu->readUniq(); -} - -template -void -AlphaDynInst::setUniq(uint64_t val) -{ - this->cpu->setUniq(val); -} - -template -uint64_t -AlphaDynInst::readFpcr() -{ - return this->cpu->readFpcr(); -} - -template -void -AlphaDynInst::setFpcr(uint64_t val) -{ - this->cpu->setFpcr(val); -} - #if FULL_SYSTEM -template -uint64_t -AlphaDynInst::readIpr(int idx, Fault &fault) -{ - return this->cpu->readIpr(idx, fault); -} - -template -Fault -AlphaDynInst::setIpr(int idx, uint64_t val) -{ - return this->cpu->setIpr(idx, val); -} - template Fault AlphaDynInst::hwrei() diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index 706657887..a8c620028 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -264,13 +264,13 @@ FullO3CPU::init() regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i]; regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i]; } - +/* // Then loop through the misc registers. regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr; regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq; regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag; regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr; - +*/ // Then finally set the PC and the next PC. regFile.pc = src_xc->regs.pc; regFile.npc = src_xc->regs.npc; diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 321d61dce..09d9c3d66 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -152,11 +152,11 @@ class FullO3CPU : public BaseFullCPU /** Get instruction asid. */ int getInstAsid() - { return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); } + { return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); } /** Get data asid. */ int getDataAsid() - { return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); } + { return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); } #else bool validInstAddr(Addr addr) { return thread[0]->validInstAddr(addr); } diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index ee7b8858e..1bc7159f6 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -56,6 +56,8 @@ class PhysRegFile typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::MiscRegFile MiscRegFile; + typedef TheISA::MiscReg MiscReg; + //Note that most of the definitions of the IntReg, FloatReg, etc. exist //within the Impl/ISA class and not within this PhysRegFile class. @@ -194,30 +196,21 @@ class PhysRegFile //Consider leaving this stuff and below in some implementation specific //file as opposed to the general register file. Or have a derived class. - uint64_t readUniq() - { - return miscRegs.uniq; - } - - void setUniq(uint64_t val) - { - miscRegs.uniq = val; - } - - uint64_t readFpcr() + MiscReg readMiscReg(int misc_reg) { - return miscRegs.fpcr; + // Dummy function for now. + // @todo: Fix this once proxy XC is used. + return 0; } - void setFpcr(uint64_t val) + Fault setMiscReg(int misc_reg, const MiscReg &val) { - miscRegs.fpcr = val; + // Dummy function for now. + // @todo: Fix this once proxy XC is used. + return NoFault; } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); - InternalProcReg *getIpr() { return ipr; } int readIntrFlag() { return intrflag; } void setIntrFlag(int val) { intrflag = val; } #endif @@ -272,368 +265,4 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs, memset(floatRegFile, 0, sizeof(*floatRegFile)); } -#if FULL_SYSTEM - -//Problem: This code doesn't make sense at the RegFile level because it -//needs things such as the itb and dtb. Either put it at the CPU level or -//the DynInst level. -template -uint64_t -PhysRegFile::readIpr(int idx, Fault &fault) -{ - uint64_t retval = 0; // return value, default 0 - - switch (idx) { - case TheISA::IPR_PALtemp0: - case TheISA::IPR_PALtemp1: - case TheISA::IPR_PALtemp2: - case TheISA::IPR_PALtemp3: - case TheISA::IPR_PALtemp4: - case TheISA::IPR_PALtemp5: - case TheISA::IPR_PALtemp6: - case TheISA::IPR_PALtemp7: - case TheISA::IPR_PALtemp8: - case TheISA::IPR_PALtemp9: - case TheISA::IPR_PALtemp10: - case TheISA::IPR_PALtemp11: - case TheISA::IPR_PALtemp12: - case TheISA::IPR_PALtemp13: - case TheISA::IPR_PALtemp14: - case TheISA::IPR_PALtemp15: - case TheISA::IPR_PALtemp16: - case TheISA::IPR_PALtemp17: - case TheISA::IPR_PALtemp18: - case TheISA::IPR_PALtemp19: - case TheISA::IPR_PALtemp20: - case TheISA::IPR_PALtemp21: - case TheISA::IPR_PALtemp22: - case TheISA::IPR_PALtemp23: - case TheISA::IPR_PAL_BASE: - - case TheISA::IPR_IVPTBR: - case TheISA::IPR_DC_MODE: - case TheISA::IPR_MAF_MODE: - case TheISA::IPR_ISR: - case TheISA::IPR_EXC_ADDR: - case TheISA::IPR_IC_PERR_STAT: - case TheISA::IPR_DC_PERR_STAT: - case TheISA::IPR_MCSR: - case TheISA::IPR_ASTRR: - case TheISA::IPR_ASTER: - case TheISA::IPR_SIRR: - case TheISA::IPR_ICSR: - case TheISA::IPR_ICM: - case TheISA::IPR_DTB_CM: - case TheISA::IPR_IPLR: - case TheISA::IPR_INTID: - case TheISA::IPR_PMCTR: - // no side-effect - retval = ipr[idx]; - break; - - case TheISA::IPR_CC: - retval |= ipr[idx] & ULL(0xffffffff00000000); - retval |= curTick & ULL(0x00000000ffffffff); - break; - - case TheISA::IPR_VA: - retval = ipr[idx]; - break; - - case TheISA::IPR_VA_FORM: - case TheISA::IPR_MM_STAT: - case TheISA::IPR_IFAULT_VA_FORM: - case TheISA::IPR_EXC_MASK: - case TheISA::IPR_EXC_SUM: - retval = ipr[idx]; - break; - - case TheISA::IPR_DTB_PTE: - { - TheISA::PTE &pte = cpu->dtb->index(1); - - retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; - retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; - retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; - retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; - retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; - retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; - retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; - } - break; - - // write only registers - case TheISA::IPR_HWINT_CLR: - case TheISA::IPR_SL_XMIT: - case TheISA::IPR_DC_FLUSH: - case TheISA::IPR_IC_FLUSH: - case TheISA::IPR_ALT_MODE: - case TheISA::IPR_DTB_IA: - case TheISA::IPR_DTB_IAP: - case TheISA::IPR_ITB_IA: - case TheISA::IPR_ITB_IAP: - fault = UnimplementedOpcodeFault; - break; - - default: - // invalid IPR - fault = UnimplementedOpcodeFault; - break; - } - - return retval; -} - -extern int break_ipl; - -template -Fault -PhysRegFile::setIpr(int idx, uint64_t val) -{ - uint64_t old; - - switch (idx) { - case TheISA::IPR_PALtemp0: - case TheISA::IPR_PALtemp1: - case TheISA::IPR_PALtemp2: - case TheISA::IPR_PALtemp3: - case TheISA::IPR_PALtemp4: - case TheISA::IPR_PALtemp5: - case TheISA::IPR_PALtemp6: - case TheISA::IPR_PALtemp7: - case TheISA::IPR_PALtemp8: - case TheISA::IPR_PALtemp9: - case TheISA::IPR_PALtemp10: - case TheISA::IPR_PALtemp11: - case TheISA::IPR_PALtemp12: - case TheISA::IPR_PALtemp13: - case TheISA::IPR_PALtemp14: - case TheISA::IPR_PALtemp15: - case TheISA::IPR_PALtemp16: - case TheISA::IPR_PALtemp17: - case TheISA::IPR_PALtemp18: - case TheISA::IPR_PALtemp19: - case TheISA::IPR_PALtemp20: - case TheISA::IPR_PALtemp21: - case TheISA::IPR_PALtemp22: - case TheISA::IPR_PAL_BASE: - case TheISA::IPR_IC_PERR_STAT: - case TheISA::IPR_DC_PERR_STAT: - case TheISA::IPR_PMCTR: - // write entire quad w/ no side-effect - ipr[idx] = val; - break; - - case TheISA::IPR_CC_CTL: - // This IPR resets the cycle counter. We assume this only - // happens once... let's verify that. - assert(ipr[idx] == 0); - ipr[idx] = 1; - break; - - case TheISA::IPR_CC: - // This IPR only writes the upper 64 bits. It's ok to write - // all 64 here since we mask out the lower 32 in rpcc (see - // isa_desc). - ipr[idx] = val; - break; - - case TheISA::IPR_PALtemp23: - // write entire quad w/ no side-effect - old = ipr[idx]; - ipr[idx] = val; - break; - - case TheISA::IPR_DTB_PTE: - // write entire quad w/ no side-effect, tag is forthcoming - ipr[idx] = val; - break; - - case TheISA::IPR_EXC_ADDR: - // second least significant bit in PC is always zero - ipr[idx] = val & ~2; - break; - - case TheISA::IPR_ASTRR: - case TheISA::IPR_ASTER: - // only write least significant four bits - privilege mask - ipr[idx] = val & 0xf; - break; - - case TheISA::IPR_IPLR: - // only write least significant five bits - interrupt level - ipr[idx] = val & 0x1f; - break; - - case TheISA::IPR_DTB_CM: - - case TheISA::IPR_ICM: - // only write two mode bits - processor mode - ipr[idx] = val & 0x18; - break; - - case TheISA::IPR_ALT_MODE: - // only write two mode bits - processor mode - ipr[idx] = val & 0x18; - break; - - case TheISA::IPR_MCSR: - // more here after optimization... - ipr[idx] = val; - break; - - case TheISA::IPR_SIRR: - // only write software interrupt mask - ipr[idx] = val & 0x7fff0; - break; - - case TheISA::IPR_ICSR: - ipr[idx] = val & ULL(0xffffff0300); - break; - - case TheISA::IPR_IVPTBR: - case TheISA::IPR_MVPTBR: - ipr[idx] = val & ULL(0xffffffffc0000000); - break; - - case TheISA::IPR_DC_TEST_CTL: - ipr[idx] = val & 0x1ffb; - break; - - case TheISA::IPR_DC_MODE: - case TheISA::IPR_MAF_MODE: - ipr[idx] = val & 0x3f; - break; - - case TheISA::IPR_ITB_ASN: - ipr[idx] = val & 0x7f0; - break; - - case TheISA::IPR_DTB_ASN: - ipr[idx] = val & ULL(0xfe00000000000000); - break; - - case TheISA::IPR_EXC_SUM: - case TheISA::IPR_EXC_MASK: - // any write to this register clears it - ipr[idx] = 0; - break; - - case TheISA::IPR_INTID: - case TheISA::IPR_SL_RCV: - case TheISA::IPR_MM_STAT: - case TheISA::IPR_ITB_PTE_TEMP: - case TheISA::IPR_DTB_PTE_TEMP: - // read-only registers - return UnimplementedOpcodeFault; - - case TheISA::IPR_HWINT_CLR: - case TheISA::IPR_SL_XMIT: - case TheISA::IPR_DC_FLUSH: - case TheISA::IPR_IC_FLUSH: - // the following are write only - ipr[idx] = val; - break; - - case TheISA::IPR_DTB_IA: - // really a control write - ipr[idx] = 0; - - cpu->dtb->flushAll(); - break; - - case TheISA::IPR_DTB_IAP: - // really a control write - ipr[idx] = 0; - - cpu->dtb->flushProcesses(); - break; - - case TheISA::IPR_DTB_IS: - // really a control write - ipr[idx] = val; - - cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN])); - break; - - case TheISA::IPR_DTB_TAG: { - struct TheISA::PTE pte; - - // FIXME: granularity hints NYI... - if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0) - panic("PTE GH field != 0"); - - // write entire quad - ipr[idx] = val; - - // construct PTE for new entry - pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]); - pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]); - pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]); - pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]); - pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]); - pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]); - pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]); - - // insert new TAG/PTE value into data TLB - cpu->dtb->insert(val, pte); - } - break; - - case TheISA::IPR_ITB_PTE: { - struct TheISA::PTE pte; - - // FIXME: granularity hints NYI... - if (ITB_PTE_GH(val) != 0) - panic("PTE GH field != 0"); - - // write entire quad - ipr[idx] = val; - - // construct PTE for new entry - pte.ppn = ITB_PTE_PPN(val); - pte.xre = ITB_PTE_XRE(val); - pte.xwe = 0; - pte.fonr = ITB_PTE_FONR(val); - pte.fonw = ITB_PTE_FONW(val); - pte.asma = ITB_PTE_ASMA(val); - pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]); - - // insert new TAG/PTE value into data TLB - cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte); - } - break; - - case TheISA::IPR_ITB_IA: - // really a control write - ipr[idx] = 0; - - cpu->itb->flushAll(); - break; - - case TheISA::IPR_ITB_IAP: - // really a control write - ipr[idx] = 0; - - cpu->itb->flushProcesses(); - break; - - case TheISA::IPR_ITB_IS: - // really a control write - ipr[idx] = val; - - cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN])); - break; - - default: - // invalid IPR - return UnimplementedOpcodeFault; - } - - // no error... - return NoFault; -} - -#endif // #if FULL_SYSTEM - #endif // __CPU_O3_CPU_REGFILE_HH__ -- cgit v1.2.3 From 2f7b8ab1ec301eaf0f1a57d3c566c3358780a117 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 16:27:01 -0500 Subject: Got rid of the fault_addr function. --HG-- extra : convert_revision : deb54cd82db47abb6d9bac76e072f2a4b1c883b2 --- cpu/o3/alpha_cpu_impl.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index c0ec1fb33..db94f8c9a 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -353,7 +353,7 @@ AlphaFullCPU::trap(Fault fault) swapPALShadow(true); this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] + - AlphaISA::fault_addr(fault) ); + ((AlphaFault *)(fault.get()))->vect()); this->regFile.setNextPC(PC + sizeof(MachInst)); } -- cgit v1.2.3 From 299efffaf5eb5fb55b2109a643e1e0e985f89ce6 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 28 Feb 2006 06:02:18 -0500 Subject: Cleaned up and slightly reorganized the Fault class heirarchy. arch/alpha/ev5.cc: Changed c style casts of Faults to dynamic_casts arch/alpha/faults.cc: AlphaFault is now an abstract class. arch/alpha/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. cpu/o3/alpha_cpu_impl.hh: Changed a c style cast to a dynamic_cast for a Fault sim/faults.hh: All generic Fault classes are now abstract. Also, MachineCheckFault and AlignmentFault inherit FaultBase as a virtual base class to help resolve ambiguities when they are multiply inherited in ISA specific classes. The override the isMachineCheckFault and isAlignmentFault functions appropriately, and provide a standard name for these faults. --HG-- extra : convert_revision : 2cb906708e3eaec4a12587484c09e50ed6ef88fc --- cpu/o3/alpha_cpu_impl.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index db94f8c9a..9b7cd8a0e 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -353,7 +353,7 @@ AlphaFullCPU::trap(Fault fault) swapPALShadow(true); this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] + - ((AlphaFault *)(fault.get()))->vect()); + (dynamic_cast(fault.get()))->vect()); this->regFile.setNextPC(PC + sizeof(MachInst)); } -- cgit v1.2.3 From 69e91d761765b84429dc069b8fa1cd3f25925688 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 1 Mar 2006 00:09:08 -0500 Subject: moved ev5_trap fully into the fault class. --HG-- extra : convert_revision : 182cdec9a4e05f55edff0c6a114844b9ad2ca8db --- cpu/o3/alpha_cpu_impl.hh | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index daa61bb1c..a1c659b51 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -302,7 +302,7 @@ template void AlphaFullCPU::trap(Fault fault) { - // Keep in mind that a trap may be initiated by fetch if there's a TLB +/* // Keep in mind that a trap may be initiated by fetch if there's a TLB // miss uint64_t PC = this->commit.readCommitPC(); @@ -318,8 +318,9 @@ AlphaFullCPU::trap(Fault fault) if (!fault->isA() || !inPalMode(PC)) this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC); - if (fault->isA() || fault->isA() /* || - fault == InterruptFault && !PC_PAL(regs.pc) */) { + if (fault->isA() || fault->isA()) + // || fault == InterruptFault && !PC_PAL(regs.pc) + { // traps... skip faulting instruction AlphaISA::MiscReg ipr_exc_addr = this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR); @@ -332,7 +333,7 @@ AlphaFullCPU::trap(Fault fault) this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) + (dynamic_cast(fault.get()))->vect()); - this->regFile.setNextPC(PC + sizeof(MachInst)); + this->regFile.setNextPC(PC + sizeof(MachInst));*/ } template -- cgit v1.2.3 From e7825aab59e03b9691d361338fba222f56446f77 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 3 Mar 2006 15:28:25 -0500 Subject: Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included. The shadow registers are folded into the normal integer registers to ease renaming indexing. Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode. arch/alpha/ev5.cc: Changes to automatically map the shadow registers if the instruction is in PAL mode. arch/alpha/isa/branch.isa: arch/alpha/isa/decoder.isa: arch/alpha/isa/fp.isa: arch/alpha/isa/int.isa: arch/alpha/isa/mem.isa: arch/alpha/isa/pal.isa: arch/alpha/isa/unimp.isa: Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits. arch/alpha/isa/main.isa: Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits. The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode. If it is, then it refers to the reg_redir table to determine the true index of the register it is using. Also include the opcdec instruction definition. arch/alpha/isa_traits.hh: Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not. Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers). Change the dependence tags to reflect the integer registers include the 8 shadow registers. Define function to make an ExtMachInst. Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU. arch/isa_parser.py: Have static insts decode on the ExtMachInst. base/remote_gdb.cc: Support the automatic remapping of shadow registers. Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices. cpu/o3/regfile.hh: Comment out the pal registers; they are now a part of the integer registers. cpu/simple/cpu.cc: Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin. cpu/static_inst.hh: Change from MachInst to ExtMachInst to support shadow register renaming. --HG-- extra : convert_revision : 1d23eabf735e297068e1917445a6348e9f8c88d5 --- cpu/o3/regfile.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/o3') diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 691a75382..03ad2da46 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -236,7 +236,7 @@ class PhysRegFile #if FULL_SYSTEM private: // This is ISA specifc stuff; remove it eventually once ISAImpl is used - IntReg palregs[NumIntRegs]; // PAL shadow registers +// IntReg palregs[NumIntRegs]; // PAL shadow registers InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs int intrflag; // interrupt flag bool pal_shadow; // using pal_shadow registers -- cgit v1.2.3 From f15e492375e8ecd42a1f0ba7ead68cfeb2b4b673 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sat, 4 Mar 2006 15:18:40 -0500 Subject: Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. The major change is renaming the old ExecContext to CPUExecContext, and creating two new classes, ExecContext (an abstract class), and ProxyExecContext (a templated class that derives from ExecContext). Code outside of the CPU continues to use ExecContext as normal (other than not being able to access variables within the XC). The CPU uses the CPUExecContext, or however else it stores its own state. It then creates a ProxyExecContext, templated on the class used to hold its state. This proxy is passed to any code outside of the CPU that needs to access the XC. This allows code outside of the CPU to use the ExecContext interface to access any state needed, without knowledge of how that state is laid out. Note that these changes will not compile without the accompanying revision to automatically rename the shadow registers. SConscript: Include new file, cpu_exec_context.cc. arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_memory.cc: arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: arch/alpha/isa/decoder.isa: arch/alpha/stacktrace.cc: arch/alpha/vtophys.cc: base/remote_gdb.cc: cpu/intr_control.cc: Avoid directly accessing objects within the XC. arch/alpha/ev5.cc: Avoid directly accessing objects within the XC. KernelStats have been moved to the BaseCPU instead of the XC. arch/alpha/isa_traits.hh: Remove clearIprs(). It wasn't used very often and it did not work well with the proxy ExecContext. cpu/base.cc: Place kernel stats within the BaseCPU instead of the ExecContext. For now comment out the profiling code sampling until its exact location is decided upon. cpu/base.hh: Kernel stats are now in the BaseCPU instead of the ExecContext. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. cpu/exetrace.cc: Remove unneeded include of exec_context.hh. cpu/intr_control.hh: cpu/o3/alpha_cpu_builder.cc: Remove unneeded include of exec_context.hh cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. Also avoid accessing anything directly from the XC. cpu/pc_event.cc: Avoid accessing objects directly from the XC. dev/tsunami_cchip.cc: Avoid accessing objects directly within the XC> kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/linux/linux_threadinfo.hh: kern/tru64/dump_mbuf.cc: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: sim/syscall_emul.cc: sim/syscall_emul.hh: Avoid accessing objects directly within the XC. kern/kernel_stats.cc: kern/kernel_stats.hh: Kernel stats no longer exist within the XC. kern/system_events.cc: Avoid accessing objects directly within the XC. Also kernel stats are now in the BaseCPU. sim/process.cc: sim/process.hh: Avoid accessing regs directly within an ExecContext. Instead use a CPUExecContext to initialize the registers and copy them over. cpu/cpu_exec_context.cc: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. cpu/cpu_exec_context.hh: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. Remove kernel stats from the ExecContext. sim/pseudo_inst.cc: Kernel stats now live within the CPU. Avoid accessing objects directly within the XC. --HG-- rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : a75393a8945c80cca225b5e9d9c22a16609efb85 --- cpu/o3/alpha_cpu.hh | 45 +++++++++++++++++++-------------------- cpu/o3/alpha_cpu_builder.cc | 1 - cpu/o3/alpha_cpu_impl.hh | 51 ++++++++++++++++++++++++--------------------- cpu/o3/cpu.cc | 33 +++++++++++++---------------- cpu/o3/cpu.hh | 21 ++++++++++--------- 5 files changed, 75 insertions(+), 76 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index 47ea532a6..75a4d72c2 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -152,13 +152,13 @@ class AlphaFullCPU : public FullO3CPU // set the register. IntReg getSyscallArg(int i) { - return this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i]; + return this->cpuXC->readIntReg(AlphaISA::ArgumentReg0 + i); } // used to shift args for indirect syscall void setSyscallArg(int i, IntReg val) { - this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i] = val; + this->cpuXC->setIntReg(AlphaISA::ArgumentReg0 + i, val); } void setSyscallReturn(int64_t return_value) @@ -169,12 +169,12 @@ class AlphaFullCPU : public FullO3CPU const int RegA3 = 19; // only place this is used if (return_value >= 0) { // no error - this->xc->regs.intRegFile[RegA3] = 0; - this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = return_value; + this->cpuXC->setIntReg(RegA3, 0); + this->cpuXC->setIntReg(AlphaISA::ReturnValueReg, return_value); } else { // got an error, return details - this->xc->regs.intRegFile[RegA3] = (IntReg) -1; - this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = -return_value; + this->cpuXC->setIntReg(RegA3, (IntReg) -1); + this->cpuXC->setIntReg(AlphaISA::ReturnValueReg, -return_value); } } @@ -208,9 +208,8 @@ class AlphaFullCPU : public FullO3CPU { #if FULL_SYSTEM && defined(TARGET_ALPHA) if (req->flags & LOCKED) { - MiscRegFile *cregs = &req->xc->regs.miscRegs; - cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr); - cregs->setReg(TheISA::Lock_Flag_DepTag, true); + req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr); + req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true); } #endif @@ -230,34 +229,34 @@ class AlphaFullCPU : public FullO3CPU Fault write(MemReqPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) - - MiscRegFile *cregs; + ExecContext *xc; // If this is a store conditional, act appropriately if (req->flags & LOCKED) { - cregs = &req->xc->regs.miscRegs; + xc = req->xc; if (req->flags & UNCACHEABLE) { // Don't update result register (see stq_c in isa_desc) req->result = 2; - req->xc->storeCondFailures = 0;//Needed? [RGD] + xc->setStCondFailures(0);//Needed? [RGD] } else { - bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag); - Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag); + bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag); + Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag); req->result = lock_flag; if (!lock_flag || ((lock_addr & ~0xf) != (req->paddr & ~0xf))) { - cregs->setReg(TheISA::Lock_Flag_DepTag, false); - if (((++req->xc->storeCondFailures) % 100000) == 0) { + xc->setMiscReg(TheISA::Lock_Flag_DepTag, false); + xc->setStCondFailures(xc->readStCondFailures() + 1); + if (((xc->readStCondFailures()) % 100000) == 0) { std::cerr << "Warning: " - << req->xc->storeCondFailures + << xc->readStCondFailures() << " consecutive store conditional failures " - << "on cpu " << req->xc->cpu_id + << "on cpu " << req->xc->readCpuId() << std::endl; } return NoFault; } - else req->xc->storeCondFailures = 0; + else xc->setStCondFailures(0); } } @@ -267,10 +266,10 @@ class AlphaFullCPU : public FullO3CPU // Conditionals would have returned above, and wouldn't fall // through. for (int i = 0; i < this->system->execContexts.size(); i++){ - cregs = &this->system->execContexts[i]->regs.miscRegs; - if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) == + xc = this->system->execContexts[i]; + if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) == (req->paddr & ~0xf)) { - cregs->setReg(TheISA::Lock_Flag_DepTag, false); + xc->setMiscReg(TheISA::Lock_Flag_DepTag, false); } } diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc index 3547fb1b5..7e687ad2b 100644 --- a/cpu/o3/alpha_cpu_builder.cc +++ b/cpu/o3/alpha_cpu_builder.cc @@ -30,7 +30,6 @@ #include "base/loader/symtab.hh" #include "base/misc.hh" #include "cpu/base.hh" -#include "cpu/exec_context.hh" #include "cpu/exetrace.hh" #include "cpu/o3/alpha_cpu.hh" #include "cpu/o3/alpha_impl.hh" diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index bd4e34914..271b542ab 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -165,7 +165,7 @@ AlphaFullCPU::copyToXC() for (int i = 0; i < AlphaISA::NumIntRegs; ++i) { renamed_reg = this->renameMap.lookup(i); - this->xc->regs.intRegFile[i] = this->regFile.readIntReg(renamed_reg); + this->cpuXC->setIntReg(i, this->regFile.readIntReg(renamed_reg)); DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n", renamed_reg, this->regFile.intRegFile[renamed_reg]); } @@ -174,21 +174,23 @@ AlphaFullCPU::copyToXC() for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) { renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag); - this->xc->regs.floatRegFile.d[i] = - this->regFile.readFloatRegDouble(renamed_reg); - this->xc->regs.floatRegFile.q[i] = - this->regFile.readFloatRegInt(renamed_reg); + this->cpuXC->setFloatRegDouble(i, + this->regFile.readFloatRegDouble(renamed_reg)); + this->cpuXC->setFloatRegInt(i, + this->regFile.readFloatRegInt(renamed_reg)); } /* - this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr; - this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq; - this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag; - this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr; + this->cpuXC->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr; + this->cpuXC->regs.miscRegs.uniq = this->regFile.miscRegs.uniq; + this->cpuXC->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag; + this->cpuXC->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr; */ - this->xc->regs.pc = this->rob.readHeadPC(); - this->xc->regs.npc = this->xc->regs.pc+4; + this->cpuXC->setPC(this->rob.readHeadPC()); + this->cpuXC->setNextPC(this->cpuXC->readPC()+4); - this->xc->func_exe_inst = this->funcExeInst; +#if !FULL_SYSTEM + this->cpuXC->setFuncExeInst(this->funcExeInst); +#endif } // This function will probably mess things up unless the ROB is empty and @@ -207,9 +209,9 @@ AlphaFullCPU::copyFromXC() DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, " "now has data %lli.\n", renamed_reg, this->regFile.intRegFile[renamed_reg], - this->xc->regs.intRegFile[i]); + this->cpuXC->readIntReg(i)); - this->regFile.setIntReg(renamed_reg, this->xc->regs.intRegFile[i]); + this->regFile.setIntReg(renamed_reg, this->cpuXC->readIntReg(i)); } // Then loop through the floating point registers. @@ -217,22 +219,23 @@ AlphaFullCPU::copyFromXC() { renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag); this->regFile.setFloatRegDouble(renamed_reg, - this->xc->regs.floatRegFile.d[i]); + this->cpuXC->readFloatRegDouble(i)); this->regFile.setFloatRegInt(renamed_reg, - this->xc->regs.floatRegFile.q[i]); + this->cpuXC->readFloatRegInt(i)); } /* // Then loop through the misc registers. - this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr; - this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq; - this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag; - this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr; + this->regFile.miscRegs.fpcr = this->cpuXC->regs.miscRegs.fpcr; + this->regFile.miscRegs.uniq = this->cpuXC->regs.miscRegs.uniq; + this->regFile.miscRegs.lock_flag = this->cpuXC->regs.miscRegs.lock_flag; + this->regFile.miscRegs.lock_addr = this->cpuXC->regs.miscRegs.lock_addr; */ // Then finally set the PC and the next PC. -// regFile.pc = xc->regs.pc; -// regFile.npc = xc->regs.npc; - - this->funcExeInst = this->xc->func_exe_inst; +// regFile.pc = cpuXC->regs.pc; +// regFile.npc = cpuXC->regs.npc; +#if !FULL_SYSTEM + this->funcExeInst = this->cpuXC->readFuncExeInst(); +#endif } #if FULL_SYSTEM diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index a8c620028..62d68bb33 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -35,10 +35,11 @@ #endif #include "sim/root.hh" +#include "cpu/cpu_exec_context.hh" +#include "cpu/exec_context.hh" #include "cpu/o3/alpha_dyn_inst.hh" #include "cpu/o3/alpha_impl.hh" #include "cpu/o3/cpu.hh" -#include "cpu/exec_context.hh" using namespace std; @@ -103,7 +104,7 @@ FullO3CPU::FullO3CPU(Params ¶ms) renameQueue(5, 5), iewQueue(5, 5), - xc(NULL), + cpuXC(NULL), globalSeqNum(1), @@ -134,8 +135,8 @@ FullO3CPU::FullO3CPU(Params ¶ms) for (int i = 0; i < this->number_of_threads; ++i) { #if FULL_SYSTEM assert(i == 0); - system->execContexts[i] = - new ExecContext(this, i, system, itb, dtb, mem); + thread[i] = new CPUExecContext(this, 0, system, itb, dtb, mem); + system->execContexts[i] = thread[i]->getProxy(); execContexts.push_back(system->execContexts[i]); #else @@ -143,21 +144,17 @@ FullO3CPU::FullO3CPU(Params ¶ms) DPRINTF(FullCPU, "FullCPU: Workload[%i]'s starting PC is %#x, " "process is %#x", i, params.workload[i]->prog_entry, thread[i]); - thread[i] = new ExecContext(this, i, params.workload[i], i); + thread[i] = new CPUExecContext(this, i, params.workload[i], i); } assert(params.workload[i]->getMemory() != NULL); assert(mem != NULL); - execContexts.push_back(thread[i]); + execContexts.push_back(thread[i]->getProxy()); #endif // !FULL_SYSTEM } // Note that this is a hack so that my code which still uses xc-> will // still work. I should remove this eventually -#if FULL_SYSTEM - xc = system->execContexts[0]; -#else - xc = thread[0]; -#endif + cpuXC = thread[0]; // The stages also need their CPU pointer setup. However this must be // done at the upper level CPU because they have pointers to the upper @@ -248,21 +245,21 @@ FullO3CPU::init() // that it can start properly. #if FULL_SYSTEM ExecContext *src_xc = system->execContexts[0]; - TheISA::initCPU(&src_xc->regs, src_xc->cpu_id); + TheISA::initCPU(src_xc, src_xc->readCpuId()); #else - ExecContext *src_xc = thread[0]; + ExecContext *src_xc = thread[0]->getProxy(); #endif // First loop through the integer registers. for (int i = 0; i < TheISA::NumIntRegs; ++i) { - regFile.intRegFile[i] = src_xc->regs.intRegFile[i]; + regFile.intRegFile[i] = src_xc->readIntReg(i); } // Then loop through the floating point registers. for (int i = 0; i < TheISA::NumFloatRegs; ++i) { - regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i]; - regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i]; + regFile.floatRegFile[i].d = src_xc->readFloatRegDouble(i); + regFile.floatRegFile[i].q = src_xc->readFloatRegInt(i); } /* // Then loop through the misc registers. @@ -272,8 +269,8 @@ FullO3CPU::init() regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr; */ // Then finally set the PC and the next PC. - regFile.pc = src_xc->regs.pc; - regFile.npc = src_xc->regs.npc; + regFile.pc = src_xc->readPC(); + regFile.npc = src_xc->readNextPC(); } } diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 09d9c3d66..45e21db7f 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -44,9 +44,9 @@ #include "base/timebuf.hh" #include "config/full_system.hh" #include "cpu/base.hh" +#include "cpu/cpu_exec_context.hh" #include "cpu/o3/comm.hh" #include "cpu/o3/cpu_policy.hh" -#include "cpu/exec_context.hh" #include "sim/process.hh" #if FULL_SYSTEM @@ -54,6 +54,7 @@ using namespace EV5; #endif +class ExecContext; class FunctionalMemory; class Process; @@ -164,8 +165,8 @@ class FullO3CPU : public BaseFullCPU bool validDataAddr(Addr addr) { return thread[0]->validDataAddr(addr); } - int getInstAsid() { return thread[0]->asid; } - int getDataAsid() { return thread[0]->asid; } + int getInstAsid() { return thread[0]->getInstAsid(); } + int getDataAsid() { return thread[0]->getDataAsid(); } #endif @@ -320,16 +321,17 @@ class FullO3CPU : public BaseFullCPU public: /** The temporary exec context to support older accessors. */ - ExecContext *xc; + CPUExecContext *cpuXC; /** Temporary function to get pointer to exec context. */ ExecContext *xcBase() { -#if FULL_SYSTEM - return system->execContexts[0]; -#else + return thread[0]->getProxy(); + } + + CPUExecContext *cpuXCBase() + { return thread[0]; -#endif } InstSeqNum globalSeqNum; @@ -344,9 +346,8 @@ class FullO3CPU : public BaseFullCPU AlphaDTB *dtb; // SWContext *swCtx; -#else - std::vector thread; #endif + std::vector thread; FunctionalMemory *mem; -- cgit v1.2.3 From 8106a804508a42455650082a83f4cdb366ca5148 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Mar 2006 14:08:01 -0500 Subject: Pushed ev5.hh out of the non-alpha code. arch/SConscript: ev5 should now be contained within alpha specific code. arch/alpha/ev5.cc: arch/alpha/isa_traits.hh: Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. arch/sparc/isa_traits.hh: Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. Also made some small fixes. cpu/o3/alpha_cpu.hh: Added typedefs which are required now that there isn't a using namespace EV5. cpu/o3/alpha_cpu_impl.hh: Some small changes so that ev5.hh isn't needed directly. cpu/o3/cpu.hh: Removed including ev5.hh, and pushed retrieving the Asid into the MiscRegFile. cpu/o3/regfile.hh: Removed the include of ev5.hh, using namespace EV5, and the now redundant ipr array. --HG-- extra : convert_revision : 5ef8f69435a3a888a3f06d0095d89326dafb33fd --- cpu/o3/alpha_cpu.hh | 2 ++ cpu/o3/alpha_cpu_impl.hh | 3 ++- cpu/o3/cpu.hh | 9 ++------- cpu/o3/regfile.hh | 3 --- 4 files changed, 6 insertions(+), 11 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index 38c00a3a9..55fde1f1d 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -42,6 +42,8 @@ class AlphaFullCPU : public FullO3CPU protected: typedef TheISA::IntReg IntReg; typedef TheISA::MiscReg MiscReg; + typedef TheISA::RegFile RegFile; + typedef TheISA::MiscRegFile MiscRegFile; public: typedef typename Impl::Params Params; diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index a1c659b51..5ab9e6e75 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include "arch/alpha/faults.hh" #include "base/cprintf.hh" #include "base/statistics.hh" #include "base/timebuf.hh" @@ -257,7 +258,7 @@ Fault AlphaFullCPU::hwrei() { if (!inPalMode()) - return new UnimplementedOpcodeFault; + return new AlphaISA::UnimplementedOpcodeFault; this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR)); diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 02908887e..31a1b604b 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -49,11 +49,6 @@ #include "cpu/exec_context.hh" #include "sim/process.hh" -#if FULL_SYSTEM -#include "arch/ev5.hh" -using namespace EV5; -#endif - class FunctionalMemory; class Process; @@ -152,11 +147,11 @@ class FullO3CPU : public BaseFullCPU /** Get instruction asid. */ int getInstAsid() - { return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); } + { return regFile.miscRegs.getInstAsid(); } /** Get data asid. */ int getDataAsid() - { return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); } + { return regFile.miscRegs.getDataAsid(); } #else bool validInstAddr(Addr addr) { return thread[0]->validInstAddr(addr); } diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 03ad2da46..1e6e10f29 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -38,10 +38,8 @@ #include "cpu/o3/comm.hh" #if FULL_SYSTEM -#include "arch/ev5.hh" #include "kern/kernel_stats.hh" -using namespace EV5; #endif // This really only depends on the ISA, and not the Impl. It might be nicer @@ -237,7 +235,6 @@ class PhysRegFile private: // This is ISA specifc stuff; remove it eventually once ISAImpl is used // IntReg palregs[NumIntRegs]; // PAL shadow registers - InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs int intrflag; // interrupt flag bool pal_shadow; // using pal_shadow registers #endif -- cgit v1.2.3 From 556d069e77f1b6dffa4e4ece7aa86ab462ab8f4f Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 7 Mar 2006 22:24:37 -0500 Subject: Fixes for accesses to the misc regs. --HG-- extra : convert_revision : 47c7d90be5a147cb644f11980adcf8165b0ab3bb --- cpu/o3/alpha_cpu_impl.hh | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) (limited to 'cpu/o3') diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 33e363d4f..30ef4bd43 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -179,12 +179,16 @@ AlphaFullCPU::copyToXC() this->cpuXC->setFloatRegInt(i, this->regFile.readFloatRegInt(renamed_reg)); } -/* - this->cpuXC->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr; - this->cpuXC->regs.miscRegs.uniq = this->regFile.miscRegs.uniq; - this->cpuXC->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag; - this->cpuXC->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr; -*/ + + this->cpuXC->setMiscReg(AlphaISA::Fpcr_DepTag, + this->regFile.readMiscReg(AlphaISA::Fpcr_DepTag)); + this->cpuXC->setMiscReg(AlphaISA::Uniq_DepTag, + this->regFile.readMiscReg(AlphaISA::Uniq_DepTag)); + this->cpuXC->setMiscReg(AlphaISA::Lock_Flag_DepTag, + this->regFile.readMiscReg(AlphaISA::Lock_Flag_DepTag)); + this->cpuXC->setMiscReg(AlphaISA::Lock_Addr_DepTag, + this->regFile.readMiscReg(AlphaISA::Lock_Addr_DepTag)); + this->cpuXC->setPC(this->rob.readHeadPC()); this->cpuXC->setNextPC(this->cpuXC->readPC()+4); @@ -223,13 +227,17 @@ AlphaFullCPU::copyFromXC() this->regFile.setFloatRegInt(renamed_reg, this->cpuXC->readFloatRegInt(i)); } - /* + // Then loop through the misc registers. - this->regFile.miscRegs.fpcr = this->cpuXC->regs.miscRegs.fpcr; - this->regFile.miscRegs.uniq = this->cpuXC->regs.miscRegs.uniq; - this->regFile.miscRegs.lock_flag = this->cpuXC->regs.miscRegs.lock_flag; - this->regFile.miscRegs.lock_addr = this->cpuXC->regs.miscRegs.lock_addr; - */ + this->regFile.setMiscReg(AlphaISA::Fpcr_DepTag, + this->cpuXC->readMiscReg(AlphaISA::Fpcr_DepTag)); + this->regFile.setMiscReg(AlphaISA::Uniq_DepTag, + this->cpuXC->readMiscReg(AlphaISA::Uniq_DepTag)); + this->regFile.setMiscReg(AlphaISA::Lock_Flag_DepTag, + this->cpuXC->readMiscReg(AlphaISA::Lock_Flag_DepTag)); + this->regFile.setMiscReg(AlphaISA::Lock_Addr_DepTag, + this->cpuXC->readMiscReg(AlphaISA::Lock_Addr_DepTag)); + // Then finally set the PC and the next PC. // regFile.pc = cpuXC->regs.pc; // regFile.npc = cpuXC->regs.npc; -- cgit v1.2.3