From f6fc18f03d639098b1421fa3412329773b0a6ab1 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Tue, 11 Apr 2006 13:42:47 -0400
Subject: fullsys now builds and runs for about one cycle
SConscript:
easier to fix than temporarily remove
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
mem needed for both fullsys and syscall
dev/baddev.cc:
fix for new mem system
dev/io_device.cc:
fix typo
dev/io_device.hh:
PioDevice needs to be a memobject
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
fix for new mem systems
dev/platform.cc:
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
rather than the platform have a pointer to pciconfig, go the other
way so all devices are the same and can have a platform pointer
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart8250.cc:
python/m5/objects/AlphaConsole.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/Device.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/System.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
fixes for newmem
--HG--
extra : convert_revision : b7b67e19095cca64889f6307725aa2f3d84c7105
---
cpu/simple/cpu.cc | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
(limited to 'cpu/simple/cpu.cc')
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 261ed8302..6fbf9d077 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -155,13 +155,8 @@ SimpleCPU::CpuPort::recvRetry()
}
SimpleCPU::SimpleCPU(Params *p)
-#if !FULL_SYSTEM
: BaseCPU(p), mem(p->mem), icachePort(this),
dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
-#else
- : BaseCPU(p), icachePort(this), dcachePort(this),
- tickEvent(this, p->width), cpuXC(NULL)
-#endif
{
_status = Idle;
@@ -1133,6 +1128,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
+ SimObjectParam<MemObject *> mem;
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
@@ -1141,7 +1137,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
Param<int> cpu_id;
Param<Tick> profile;
#else
- SimObjectParam<MemObject *> mem;
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
@@ -1164,6 +1159,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
+ INIT_PARAM(mem, "memory"),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
@@ -1172,7 +1168,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(profile, ""),
#else
- INIT_PARAM(mem, "memory"),
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
@@ -1199,6 +1194,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
params->width = width;
+ params->mem = mem;
#if FULL_SYSTEM
params->itb = itb;
@@ -1207,7 +1203,6 @@ CREATE_SIM_OBJECT(SimpleCPU)
params->cpu_id = cpu_id;
params->profile = profile;
#else
- params->mem = mem;
params->process = workload;
#endif
--
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