From 2939a7089ad89e38b24f96143dbd3c4292ac0287 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Feb 2006 00:16:44 -0500 Subject: byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions. arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: Added the endianness namespace. This may change. cpu/exec_context.hh: Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution. cpu/o3/alpha_cpu.hh: Forced LittleEndianness, for lack of a better solution. cpu/o3/alpha_cpu_impl.hh: Cleared away some commented out code. cpu/o3/fetch_impl.hh: Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution. cpu/simple/cpu.cc: Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine. dev/disk_image.cc: Changed the include path of byteswap.hh kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution. sim/system.cc: Forced LittleEndianness for lack of a better solution. --HG-- extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206 --- cpu/simple/cpu.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index a7f4fa499..70217f0bb 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -54,6 +54,7 @@ #include "kern/kernel_stats.hh" #include "mem/base_mem.hh" #include "mem/mem_interface.hh" +#include "sim/byteswap.hh" #include "sim/builder.hh" #include "sim/debug.hh" #include "sim/host.hh" @@ -74,6 +75,8 @@ #endif // FULL_SYSTEM using namespace std; +//The SimpleCPU does alpha only +using namespace LittleEndianGuest; SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w) -- cgit v1.2.3 From 10c79efe556697ebbed74c82214b5505b405da5b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 16 Feb 2006 01:22:51 -0500 Subject: Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA. SConscript: The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away. arch/alpha/alpha_memory.cc: Changed Fault to Fault * and took the underscores out of fault names. arch/alpha/alpha_memory.hh: Changed Fault to Fault *. Also, added an include for the alpha faults. arch/alpha/ev5.cc: Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names. arch/alpha/isa/decoder.isa: Changed Fault to Fault * and took the underscores out fault names. arch/alpha/isa/fp.isa: Changed Fault to Fault *, and took the underscores out of fault names. arch/alpha/isa/main.isa: Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files. arch/alpha/isa/mem.isa: Changed Fault to Fault * and removed underscores from fault names. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: cpu/exec_context.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: dev/alpha_console.cc: dev/ide_ctrl.cc: dev/isa_fake.cc: dev/pciconfigall.cc: dev/pcidev.cc: dev/pcidev.hh: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Changed Fault to Fault *, and removed underscores from fault names. arch/alpha/isa_traits.hh: Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed. cpu/base_dyn_inst.cc: Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault. cpu/base_dyn_inst.hh: Changed Fault to Fault * and took the underscores out of the fault names. cpu/exec_context.cc: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/fetch.hh: dev/alpha_console.hh: dev/baddev.hh: dev/ide_ctrl.hh: dev/isa_fake.hh: dev/ns_gige.hh: dev/pciconfigall.hh: dev/sinic.hh: dev/tsunami_cchip.hh: dev/tsunami_io.hh: dev/tsunami_pchip.hh: dev/uart.hh: dev/uart8250.hh: Changed Fault to Fault *. cpu/o3/alpha_cpu.hh: Changed Fault to Fault *, removed underscores from fault names. cpu/o3/alpha_cpu_impl.hh: Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away. cpu/o3/commit_impl.hh: cpu/o3/fetch_impl.hh: dev/baddev.cc: Changed Fault to Fault *, and removed underscores from the fault names. cpu/o3/regfile.hh: Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names. cpu/simple/cpu.hh: Changed Fault to Fault * dev/ns_gige.cc: Changed Fault to Fault *, and removdd underscores from fault names. dev/sinic.cc: Changed Fault to Fault *, and removed the underscores from fault names. dev/uart8250.cc: Chanted Fault to Fault *, and removed underscores from fault names. kern/kernel_stats.cc: Removed underscores from fault names, and from NumFaults. kern/kernel_stats.hh: Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally. sim/faults.cc: This allocates the system wide faults. sim/faults.hh: This declares the system wide faults. sim/syscall_emul.cc: sim/syscall_emul.hh: Removed the underscores from fault names. --HG-- rename : arch/alpha/faults.cc => sim/faults.cc rename : arch/alpha/faults.hh => sim/faults.hh extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d --- cpu/simple/cpu.cc | 78 +++++++++++++++++++++++++++---------------------------- cpu/simple/cpu.hh | 16 ++++++------ 2 files changed, 47 insertions(+), 47 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 70217f0bb..6aff94abd 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -312,7 +312,7 @@ change_thread_state(int thread_number, int activate, int priority) { } -Fault +Fault * SimpleCPU::copySrcTranslate(Addr src) { static bool no_warn = true; @@ -332,11 +332,11 @@ SimpleCPU::copySrcTranslate(Addr src) memReq->reset(src & ~(blk_size - 1), blk_size); // translate to physical address - Fault fault = xc->translateDataReadReq(memReq); + Fault * fault = xc->translateDataReadReq(memReq); - assert(fault != Alignment_Fault); + assert(fault != AlignmentFault); - if (fault == No_Fault) { + if (fault == NoFault) { xc->copySrcAddr = src; xc->copySrcPhysAddr = memReq->paddr + offset; } else { @@ -346,7 +346,7 @@ SimpleCPU::copySrcTranslate(Addr src) return fault; } -Fault +Fault * SimpleCPU::copy(Addr dest) { static bool no_warn = true; @@ -367,11 +367,11 @@ SimpleCPU::copy(Addr dest) memReq->reset(dest & ~(blk_size -1), blk_size); // translate to physical address - Fault fault = xc->translateDataWriteReq(memReq); + Fault * fault = xc->translateDataWriteReq(memReq); - assert(fault != Alignment_Fault); + assert(fault != AlignmentFault); - if (fault == No_Fault) { + if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; // Need to read straight from memory since we have more than 8 bytes. memReq->paddr = xc->copySrcPhysAddr; @@ -394,11 +394,11 @@ SimpleCPU::copy(Addr dest) // precise architected memory state accessor macros template -Fault +Fault * SimpleCPU::read(Addr addr, T &data, unsigned flags) { if (status() == DcacheMissStall || status() == DcacheMissSwitch) { - Fault fault = xc->read(memReq,data); + Fault * fault = xc->read(memReq,data); if (traceData) { traceData->setAddr(addr); @@ -409,10 +409,10 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault fault = xc->translateDataReadReq(memReq); + Fault * fault = xc->translateDataReadReq(memReq); // if we have a cache, do cache access too - if (fault == No_Fault && dcacheInterface) { + if (fault == NoFault && dcacheInterface) { memReq->cmd = Read; memReq->completionEvent = NULL; memReq->time = curTick; @@ -432,7 +432,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) fault = xc->read(memReq, data); } - } else if(fault == No_Fault) { + } else if(fault == NoFault) { // do functional access fault = xc->read(memReq, data); @@ -447,32 +447,32 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) #ifndef DOXYGEN_SHOULD_SKIP_THIS template -Fault +Fault * SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); template -Fault +Fault * SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); template -Fault +Fault * SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); template -Fault +Fault * SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); #endif //DOXYGEN_SHOULD_SKIP_THIS template<> -Fault +Fault * SimpleCPU::read(Addr addr, double &data, unsigned flags) { return read(addr, *(uint64_t*)&data, flags); } template<> -Fault +Fault * SimpleCPU::read(Addr addr, float &data, unsigned flags) { return read(addr, *(uint32_t*)&data, flags); @@ -480,7 +480,7 @@ SimpleCPU::read(Addr addr, float &data, unsigned flags) template<> -Fault +Fault * SimpleCPU::read(Addr addr, int32_t &data, unsigned flags) { return read(addr, (uint32_t&)data, flags); @@ -488,19 +488,19 @@ SimpleCPU::read(Addr addr, int32_t &data, unsigned flags) template -Fault +Fault * SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) { memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault fault = xc->translateDataWriteReq(memReq); + Fault * fault = xc->translateDataWriteReq(memReq); // do functional access - if (fault == No_Fault) + if (fault == NoFault) fault = xc->write(memReq, data); - if (fault == No_Fault && dcacheInterface) { + if (fault == NoFault && dcacheInterface) { memReq->cmd = Write; memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; @@ -519,7 +519,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) } } - if (res && (fault == No_Fault)) + if (res && (fault == NoFault)) *res = memReq->result; if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) @@ -531,32 +531,32 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) #ifndef DOXYGEN_SHOULD_SKIP_THIS template -Fault +Fault * SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res); template -Fault +Fault * SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res); template -Fault +Fault * SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res); template -Fault +Fault * SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res); #endif //DOXYGEN_SHOULD_SKIP_THIS template<> -Fault +Fault * SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) { return write(*(uint64_t*)&data, addr, flags, res); } template<> -Fault +Fault * SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) { return write(*(uint32_t*)&data, addr, flags, res); @@ -564,7 +564,7 @@ SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) template<> -Fault +Fault * SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) { return write((uint32_t)data, addr, flags, res); @@ -638,7 +638,7 @@ SimpleCPU::tick() traceData = NULL; - Fault fault = No_Fault; + Fault * fault = NoFault; #if FULL_SYSTEM if (checkInterrupts && check_interrupts() && !xc->inPalMode() && @@ -675,7 +675,7 @@ SimpleCPU::tick() if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) { ipr[TheISA::IPR_ISR] = summary; ipr[TheISA::IPR_INTID] = ipl; - xc->ev5_trap(Interrupt_Fault); + xc->ev5_trap(InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", ipr[TheISA::IPR_IPLR], ipl, summary); @@ -713,10 +713,10 @@ SimpleCPU::tick() fault = xc->translateInstReq(memReq); - if (fault == No_Fault) + if (fault == NoFault) fault = xc->mem->read(memReq, inst); - if (icacheInterface && fault == No_Fault) { + if (icacheInterface && fault == NoFault) { memReq->completionEvent = NULL; memReq->time = curTick; @@ -738,7 +738,7 @@ SimpleCPU::tick() // If we've got a valid instruction (i.e., no fault on instruction // fetch), then execute it. - if (fault == No_Fault) { + if (fault == NoFault) { // keep an instruction count numInst++; @@ -795,9 +795,9 @@ SimpleCPU::tick() traceFunctions(xc->regs.pc); - } // if (fault == No_Fault) + } // if (fault == NoFault) - if (fault != No_Fault) { + if (fault != NoFault) { #if FULL_SYSTEM xc->ev5_trap(fault); #else // !FULL_SYSTEM diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index 0f7251237..e7a447117 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -234,10 +234,10 @@ class SimpleCPU : public BaseCPU virtual void unserialize(Checkpoint *cp, const std::string §ion); template - Fault read(Addr addr, T &data, unsigned flags); + Fault * read(Addr addr, T &data, unsigned flags); template - Fault write(T data, Addr addr, unsigned flags, uint64_t *res); + Fault * write(T data, Addr addr, unsigned flags, uint64_t *res); // These functions are only used in CPU models that split // effective address computation from the actual memory access. @@ -254,9 +254,9 @@ class SimpleCPU : public BaseCPU // need to do this... } - Fault copySrcTranslate(Addr src); + Fault * copySrcTranslate(Addr src); - Fault copy(Addr dest); + Fault * copy(Addr dest); // The register accessor methods provide the index of the // instruction's operand (e.g., 0 or 1), not the architectural @@ -325,13 +325,13 @@ class SimpleCPU : public BaseCPU void setFpcr(uint64_t val) { xc->setFpcr(val); } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); } - Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } - Fault hwrei() { return xc->hwrei(); } + uint64_t readIpr(int idx, Fault * &fault) { return xc->readIpr(idx, fault); } + Fault * setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } + Fault * hwrei() { return xc->hwrei(); } int readIntrFlag() { return xc->readIntrFlag(); } void setIntrFlag(int val) { xc->setIntrFlag(val); } bool inPalMode() { return xc->inPalMode(); } - void ev5_trap(Fault fault) { xc->ev5_trap(fault); } + void ev5_trap(Fault * fault) { xc->ev5_trap(fault); } bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } #else void syscall() { xc->syscall(); } -- cgit v1.2.3 From 463aa6d49d49ba9c383f07207df57bad75c58ec9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 19 Feb 2006 02:34:37 -0500 Subject: Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45 --- cpu/simple/cpu.cc | 34 +++++++++++++++++----------------- cpu/simple/cpu.hh | 20 +++++++++++--------- 2 files changed, 28 insertions(+), 26 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 6aff94abd..c3f256de9 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -76,7 +76,7 @@ using namespace std; //The SimpleCPU does alpha only -using namespace LittleEndianGuest; +using namespace AlphaISA; SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w) @@ -125,7 +125,7 @@ SimpleCPU::SimpleCPU(Params *p) xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); // initialize CPU, including PC - TheISA::initCPU(&xc->regs); + initCPU(&xc->regs); #else xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0); #endif // !FULL_SYSTEM @@ -323,7 +323,7 @@ SimpleCPU::copySrcTranslate(Addr src) // Make sure block doesn't span page if (no_warn && - (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) && + (src & PageMask) != ((src + blk_size) & PageMask) && (src >> 40) != 0xfffffc) { warn("Copied block source spans pages %x.", src); no_warn = false; @@ -359,7 +359,7 @@ SimpleCPU::copy(Addr dest) // Make sure block doesn't span page if (no_warn && - (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) && + (dest & PageMask) != ((dest + blk_size) & PageMask) && (dest >> 40) != 0xfffffc) { no_warn = false; warn("Copied block destination spans pages %x. ", dest); @@ -648,20 +648,20 @@ SimpleCPU::tick() checkInterrupts = false; IntReg *ipr = xc->regs.ipr; - if (xc->regs.ipr[TheISA::IPR_SIRR]) { - for (int i = TheISA::INTLEVEL_SOFTWARE_MIN; - i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) { - if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) { + if (xc->regs.ipr[IPR_SIRR]) { + for (int i = INTLEVEL_SOFTWARE_MIN; + i < INTLEVEL_SOFTWARE_MAX; i++) { + if (ipr[IPR_SIRR] & (ULL(1) << i)) { // See table 4-19 of 21164 hardware reference - ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1; + ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); } } } uint64_t interrupts = xc->cpu->intr_status(); - for (int i = TheISA::INTLEVEL_EXTERNAL_MIN; - i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) { + for (int i = INTLEVEL_EXTERNAL_MIN; + i < INTLEVEL_EXTERNAL_MAX; i++) { if (interrupts & (ULL(1) << i)) { // See table 4-19 of 21164 hardware reference ipl = i; @@ -669,16 +669,16 @@ SimpleCPU::tick() } } - if (ipr[TheISA::IPR_ASTRR]) + if (ipr[IPR_ASTRR]) panic("asynchronous traps not implemented\n"); - if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) { - ipr[TheISA::IPR_ISR] = summary; - ipr[TheISA::IPR_INTID] = ipl; + if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) { + ipr[IPR_ISR] = summary; + ipr[IPR_INTID] = ipl; xc->ev5_trap(InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - ipr[TheISA::IPR_IPLR], ipl, summary); + ipr[IPR_IPLR], ipl, summary); } } #endif @@ -749,7 +749,7 @@ SimpleCPU::tick() // decode the instruction inst = gtoh(inst); - curStaticInst = StaticInst::decode(inst); + curStaticInst = StaticInst::decode(inst); traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst, xc->regs.pc); diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index e7a447117..8a3900726 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -63,6 +63,8 @@ namespace Trace { class SimpleCPU : public BaseCPU { + protected: + typedef TheISA::MachInst MachInst; public: // main simulation loop (one cycle) void tick(); @@ -172,7 +174,7 @@ class SimpleCPU : public BaseCPU // the next switchover Sampler *sampler; - StaticInstPtr curStaticInst; + StaticInstPtr curStaticInst; class CacheCompletionEvent : public Event { @@ -269,47 +271,47 @@ class SimpleCPU : public BaseCPU // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst *si, int idx) + uint64_t readIntReg(const StaticInst *si, int idx) { return xc->readIntReg(si->srcRegIdx(idx)); } - float readFloatRegSingle(const StaticInst *si, int idx) + float readFloatRegSingle(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegSingle(reg_idx); } - double readFloatRegDouble(const StaticInst *si, int idx) + double readFloatRegDouble(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegDouble(reg_idx); } - uint64_t readFloatRegInt(const StaticInst *si, int idx) + uint64_t readFloatRegInt(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegInt(reg_idx); } - void setIntReg(const StaticInst *si, int idx, uint64_t val) + void setIntReg(const StaticInst *si, int idx, uint64_t val) { xc->setIntReg(si->destRegIdx(idx), val); } - void setFloatRegSingle(const StaticInst *si, int idx, float val) + void setFloatRegSingle(const StaticInst *si, int idx, float val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegSingle(reg_idx, val); } - void setFloatRegDouble(const StaticInst *si, int idx, double val) + void setFloatRegDouble(const StaticInst *si, int idx, double val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegDouble(reg_idx, val); } - void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) + void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegInt(reg_idx, val); -- cgit v1.2.3 From 8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 21 Feb 2006 20:10:40 -0500 Subject: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. --HG-- extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb --- cpu/simple/cpu.cc | 48 ++++++++++++++++++++++++------------------------ cpu/simple/cpu.hh | 16 ++++++++-------- 2 files changed, 32 insertions(+), 32 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index c3f256de9..f7a6d2c21 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -312,7 +312,7 @@ change_thread_state(int thread_number, int activate, int priority) { } -Fault * +Fault SimpleCPU::copySrcTranslate(Addr src) { static bool no_warn = true; @@ -332,7 +332,7 @@ SimpleCPU::copySrcTranslate(Addr src) memReq->reset(src & ~(blk_size - 1), blk_size); // translate to physical address - Fault * fault = xc->translateDataReadReq(memReq); + Fault fault = xc->translateDataReadReq(memReq); assert(fault != AlignmentFault); @@ -346,7 +346,7 @@ SimpleCPU::copySrcTranslate(Addr src) return fault; } -Fault * +Fault SimpleCPU::copy(Addr dest) { static bool no_warn = true; @@ -367,7 +367,7 @@ SimpleCPU::copy(Addr dest) memReq->reset(dest & ~(blk_size -1), blk_size); // translate to physical address - Fault * fault = xc->translateDataWriteReq(memReq); + Fault fault = xc->translateDataWriteReq(memReq); assert(fault != AlignmentFault); @@ -394,11 +394,11 @@ SimpleCPU::copy(Addr dest) // precise architected memory state accessor macros template -Fault * +Fault SimpleCPU::read(Addr addr, T &data, unsigned flags) { if (status() == DcacheMissStall || status() == DcacheMissSwitch) { - Fault * fault = xc->read(memReq,data); + Fault fault = xc->read(memReq,data); if (traceData) { traceData->setAddr(addr); @@ -409,7 +409,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault * fault = xc->translateDataReadReq(memReq); + Fault fault = xc->translateDataReadReq(memReq); // if we have a cache, do cache access too if (fault == NoFault && dcacheInterface) { @@ -447,32 +447,32 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) #ifndef DOXYGEN_SHOULD_SKIP_THIS template -Fault * +Fault SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); template -Fault * +Fault SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); template -Fault * +Fault SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); template -Fault * +Fault SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); #endif //DOXYGEN_SHOULD_SKIP_THIS template<> -Fault * +Fault SimpleCPU::read(Addr addr, double &data, unsigned flags) { return read(addr, *(uint64_t*)&data, flags); } template<> -Fault * +Fault SimpleCPU::read(Addr addr, float &data, unsigned flags) { return read(addr, *(uint32_t*)&data, flags); @@ -480,7 +480,7 @@ SimpleCPU::read(Addr addr, float &data, unsigned flags) template<> -Fault * +Fault SimpleCPU::read(Addr addr, int32_t &data, unsigned flags) { return read(addr, (uint32_t&)data, flags); @@ -488,13 +488,13 @@ SimpleCPU::read(Addr addr, int32_t &data, unsigned flags) template -Fault * +Fault SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) { memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault * fault = xc->translateDataWriteReq(memReq); + Fault fault = xc->translateDataWriteReq(memReq); // do functional access if (fault == NoFault) @@ -531,32 +531,32 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) #ifndef DOXYGEN_SHOULD_SKIP_THIS template -Fault * +Fault SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res); template -Fault * +Fault SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res); template -Fault * +Fault SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res); template -Fault * +Fault SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res); #endif //DOXYGEN_SHOULD_SKIP_THIS template<> -Fault * +Fault SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) { return write(*(uint64_t*)&data, addr, flags, res); } template<> -Fault * +Fault SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) { return write(*(uint32_t*)&data, addr, flags, res); @@ -564,7 +564,7 @@ SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) template<> -Fault * +Fault SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) { return write((uint32_t)data, addr, flags, res); @@ -638,7 +638,7 @@ SimpleCPU::tick() traceData = NULL; - Fault * fault = NoFault; + Fault fault = NoFault; #if FULL_SYSTEM if (checkInterrupts && check_interrupts() && !xc->inPalMode() && diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index 8a3900726..d3e0323b6 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -236,10 +236,10 @@ class SimpleCPU : public BaseCPU virtual void unserialize(Checkpoint *cp, const std::string §ion); template - Fault * read(Addr addr, T &data, unsigned flags); + Fault read(Addr addr, T &data, unsigned flags); template - Fault * write(T data, Addr addr, unsigned flags, uint64_t *res); + Fault write(T data, Addr addr, unsigned flags, uint64_t *res); // These functions are only used in CPU models that split // effective address computation from the actual memory access. @@ -256,9 +256,9 @@ class SimpleCPU : public BaseCPU // need to do this... } - Fault * copySrcTranslate(Addr src); + Fault copySrcTranslate(Addr src); - Fault * copy(Addr dest); + Fault copy(Addr dest); // The register accessor methods provide the index of the // instruction's operand (e.g., 0 or 1), not the architectural @@ -327,13 +327,13 @@ class SimpleCPU : public BaseCPU void setFpcr(uint64_t val) { xc->setFpcr(val); } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault * &fault) { return xc->readIpr(idx, fault); } - Fault * setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } - Fault * hwrei() { return xc->hwrei(); } + uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); } + Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } + Fault hwrei() { return xc->hwrei(); } int readIntrFlag() { return xc->readIntrFlag(); } void setIntrFlag(int val) { xc->setIntrFlag(val); } bool inPalMode() { return xc->inPalMode(); } - void ev5_trap(Fault * fault) { xc->ev5_trap(fault); } + void ev5_trap(Fault fault) { xc->ev5_trap(fault); } bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } #else void syscall() { xc->syscall(); } -- cgit v1.2.3 From 1166d4f0bfe67a9dc178be3454b4f0eac38663ad Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 23 Feb 2006 14:50:16 -0500 Subject: Get rid of the xc from the alphaAccess/alphaConsole backdoor device. Now allocate an array of stacks indexed by cpu number which specify cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for their stacks before continuing. This change *REQUIRES* a the new console code to operate correctly. arch/alpha/ev5.cc: Add cpuId to initCPU/initIPR functions cpu/o3/cpu.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Move the cpu initilization into an init() function since it now needs the CPU id which isn't known at construction dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: instead of the bootstrap variables, add space for 64 cpu stacks in the alpha access structure. sim/system.cc: start all cpus immediately rather than just the first one --HG-- extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b --- cpu/simple/cpu.cc | 17 +++++++++++++++-- cpu/simple/cpu.hh | 1 + 2 files changed, 16 insertions(+), 2 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 70217f0bb..2438e49f6 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -84,6 +84,21 @@ SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w) { } + +void +SimpleCPU::init() +{ + BaseCPU::init(); +#if FULL_SYSTEM + for (int i = 0; i < execContexts.size(); ++i) { + ExecContext *xc = execContexts[i]; + + // initialize CPU, including PC + TheISA::initCPU(&xc->regs, xc->cpu_id); + } +#endif +} + void SimpleCPU::TickEvent::process() { @@ -124,8 +139,6 @@ SimpleCPU::SimpleCPU(Params *p) #if FULL_SYSTEM xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); - // initialize CPU, including PC - TheISA::initCPU(&xc->regs); #else xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0); #endif // !FULL_SYSTEM diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index 0f7251237..564749592 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -66,6 +66,7 @@ class SimpleCPU : public BaseCPU public: // main simulation loop (one cycle) void tick(); + virtual void init(); private: struct TickEvent : public Event -- cgit v1.2.3 From 08637efadc40a1003d68bba91dedb007fe10798c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 24 Feb 2006 01:51:45 -0500 Subject: Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type. arch/alpha/alpha_memory.cc: arch/alpha/isa/decoder.isa: Added news where faults are created. arch/alpha/ev5.cc: Changed places where a fault was compared to a fault type to use isA rather than == arch/alpha/faults.cc: arch/alpha/faults.hh: Changed Fault to be a RefCountingPtr arch/alpha/isa/fp.isa: Added a new where a FloatEnableFault was created. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: Added a new where an UnimplementedFault is created. base/refcnt.hh: Added include of stddef.h for the NULL macro cpu/base_dyn_inst.cc: Added a new where an UnimplementedOpcodeFault is created. cpu/o3/alpha_cpu_impl.hh: Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name() cpu/o3/regfile.hh: Added new where UnimplementedOpcodeFaults are created. cpu/simple/cpu.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created. dev/alpha_console.cc: Added news where MachineCheckFaults are created. dev/pcidev.hh: Added news where MachineCheckFaults are generated. dev/sinic.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables. kern/kernel_stats.cc: Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future. kern/kernel_stats.hh: Commented out the declaration of _fault. when fault() is called, the fault increments its own stat. sim/faults.cc: sim/faults.hh: Changed Fault from a FaultBase * to a RefCountingPtr. --HG-- extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d --- cpu/simple/cpu.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index f7a6d2c21..d6f2ffd9f 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -334,7 +334,7 @@ SimpleCPU::copySrcTranslate(Addr src) // translate to physical address Fault fault = xc->translateDataReadReq(memReq); - assert(fault != AlignmentFault); + assert(!fault->isA()); if (fault == NoFault) { xc->copySrcAddr = src; @@ -369,7 +369,7 @@ SimpleCPU::copy(Addr dest) // translate to physical address Fault fault = xc->translateDataWriteReq(memReq); - assert(fault != AlignmentFault); + assert(!fault->isA()); if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; @@ -675,7 +675,7 @@ SimpleCPU::tick() if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) { ipr[IPR_ISR] = summary; ipr[IPR_INTID] = ipl; - xc->ev5_trap(InterruptFault); + xc->ev5_trap(new InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", ipr[IPR_IPLR], ipl, summary); -- cgit v1.2.3 From 07cd7e966e6ee6715345b2f6ed2d4ea849fc7a36 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 04:02:45 -0500 Subject: Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class, and replaced the isA templated function with them where appropriate. arch/alpha/ev5.cc: cpu/simple/cpu.cc: Changed from the isA templated function to isMachineCheckFault and isAlignmentFault sim/faults.hh: Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class. --HG-- extra : convert_revision : 3bf3a4369bc24a039648ee4f2a9c1663362ff2e2 --- cpu/simple/cpu.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index a0a37f45a..4693c78c9 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -347,7 +347,7 @@ SimpleCPU::copySrcTranslate(Addr src) // translate to physical address Fault fault = xc->translateDataReadReq(memReq); - assert(!fault->isA()); + assert(!fault->isAlignmentFault()); if (fault == NoFault) { xc->copySrcAddr = src; @@ -382,7 +382,7 @@ SimpleCPU::copy(Addr dest) // translate to physical address Fault fault = xc->translateDataWriteReq(memReq); - assert(!fault->isA()); + assert(!fault->isAlignmentFault()); if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; -- cgit v1.2.3 From c5dcd152f264a837f50d39f98d0f4f81478e3553 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 05:35:43 -0500 Subject: Changed targetarch to just arch. SConscript: Changed all of the "targetarch" files to be "arch" files arch/SConscript: Added all of the remaining targetarch files to isa_switch_hdrs --HG-- extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480 --- cpu/simple/cpu.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 4693c78c9..02ecbb12c 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -67,9 +67,9 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" -#include "targetarch/stacktrace.hh" -#include "targetarch/vtophys.hh" +#include "arch/alpha_memory.hh" +#include "arch/stacktrace.hh" +#include "arch/vtophys.hh" #else // !FULL_SYSTEM #include "mem/functional/functional.hh" #endif // FULL_SYSTEM -- cgit v1.2.3 From f1ef4a8f06184df55e26268381cb4f8f56b77a50 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 06:05:10 -0500 Subject: Renamed arch files to remove alpha prefix, and changed alpha_memory.hh and cc to a more accurate tlb.hh and cc --HG-- rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/tlb.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh extra : convert_revision : 9fe6863cc37347d2a6bd716c529b0a4a50b36ea7 --- cpu/simple/cpu.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 02ecbb12c..4b0eda386 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -67,7 +67,7 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "arch/alpha_memory.hh" +#include "arch/tlb.hh" #include "arch/stacktrace.hh" #include "arch/vtophys.hh" #else // !FULL_SYSTEM -- cgit v1.2.3 From 70b35bab5778799805fe9b6040b23eb1885dbfc3 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 27 Feb 2006 11:44:35 -0500 Subject: Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs. They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76 --- cpu/simple/cpu.cc | 17 ++++++++--------- cpu/simple/cpu.hh | 25 +++++++++++++++++++------ 2 files changed, 27 insertions(+), 15 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 944bdbb0a..dd2d53c17 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -659,12 +659,11 @@ SimpleCPU::tick() int ipl = 0; int summary = 0; checkInterrupts = false; - IntReg *ipr = xc->regs.ipr; - if (xc->regs.ipr[IPR_SIRR]) { + if (xc->readMiscReg(IPR_SIRR)) { for (int i = INTLEVEL_SOFTWARE_MIN; i < INTLEVEL_SOFTWARE_MAX; i++) { - if (ipr[IPR_SIRR] & (ULL(1) << i)) { + if (xc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { // See table 4-19 of 21164 hardware reference ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); @@ -682,16 +681,16 @@ SimpleCPU::tick() } } - if (ipr[IPR_ASTRR]) + if (xc->readMiscReg(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); - if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) { - ipr[IPR_ISR] = summary; - ipr[IPR_INTID] = ipl; + if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) { + xc->setMiscReg(IPR_ISR, summary); + xc->setMiscReg(IPR_INTID, ipl); xc->ev5_trap(InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - ipr[IPR_IPLR], ipl, summary); + xc->readMiscReg(IPR_IPLR), ipl, summary); } } #endif @@ -782,7 +781,7 @@ SimpleCPU::tick() } if (xc->profile) { - bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0; + bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; xc->profilePC = usermode ? 1 : xc->regs.pc; ProfileNode *node = xc->profile->consume(xc, inst); if (node) diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index ed7b1e29b..3bc905be1 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -65,6 +65,7 @@ class SimpleCPU : public BaseCPU { protected: typedef TheISA::MachInst MachInst; + typedef TheISA::MiscReg MiscReg; public: // main simulation loop (one cycle) void tick(); @@ -321,15 +322,27 @@ class SimpleCPU : public BaseCPU uint64_t readPC() { return xc->readPC(); } void setNextPC(uint64_t val) { xc->setNextPC(val); } - uint64_t readUniq() { return xc->readUniq(); } - void setUniq(uint64_t val) { xc->setUniq(val); } + MiscReg readMiscReg(int misc_reg) + { + return xc->readMiscReg(misc_reg); + } + + MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + { + return xc->readMiscRegWithEffect(misc_reg, fault); + } - uint64_t readFpcr() { return xc->readFpcr(); } - void setFpcr(uint64_t val) { xc->setFpcr(val); } + Fault setMiscReg(int misc_reg, const MiscReg &val) + { + return xc->setMiscReg(misc_reg, val); + } + + Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + { + return xc->setMiscRegWithEffect(misc_reg, val); + } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); } - Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } Fault hwrei() { return xc->hwrei(); } int readIntrFlag() { return xc->readIntrFlag(); } void setIntrFlag(int val) { xc->setIntrFlag(val); } -- cgit v1.2.3 From 6165419d356fb0cdbcb70d22dcd2f32e689eb7db Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 23:26:13 -0500 Subject: Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context. --HG-- extra : convert_revision : 56e33536cdd9079ace03896b85ea3c84b6eb4e57 --- cpu/simple/cpu.cc | 4 ++-- cpu/simple/cpu.hh | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 4b0eda386..1f362876f 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -688,7 +688,7 @@ SimpleCPU::tick() if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) { ipr[IPR_ISR] = summary; ipr[IPR_INTID] = ipl; - xc->ev5_trap(new InterruptFault); + (new InterruptFault)->ev5_trap(xc); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", ipr[IPR_IPLR], ipl, summary); @@ -812,7 +812,7 @@ SimpleCPU::tick() if (fault != NoFault) { #if FULL_SYSTEM - xc->ev5_trap(fault); + fault->ev5_trap(xc); #else // !FULL_SYSTEM fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc); #endif // FULL_SYSTEM diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index ed7b1e29b..c58b3c5ba 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -334,7 +334,7 @@ class SimpleCPU : public BaseCPU int readIntrFlag() { return xc->readIntrFlag(); } void setIntrFlag(int val) { xc->setIntrFlag(val); } bool inPalMode() { return xc->inPalMode(); } - void ev5_trap(Fault fault) { xc->ev5_trap(fault); } + void ev5_trap(Fault fault) { fault->ev5_trap(xc); } bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } #else void syscall() { xc->syscall(); } -- cgit v1.2.3 From d6c06571169603a37321af07b4d012f05806ad26 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 1 Mar 2006 00:14:09 -0500 Subject: Used the Fault constructor to create Interrupt faults. Using the pointer directly prevents reference counting from working correctly. cpu/simple/cpu.cc: Used the Fault constructor to create an Interrupt fault. --HG-- extra : convert_revision : ec2ef7e3cd04ee9a44628877dc6e770fb907104b --- cpu/simple/cpu.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index d826c589e..e5c2e18cf 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -687,7 +687,7 @@ SimpleCPU::tick() if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) { xc->setMiscReg(IPR_ISR, summary); xc->setMiscReg(IPR_INTID, ipl); - (new InterruptFault)->ev5_trap(xc); + Fault(new InterruptFault)->ev5_trap(xc); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", xc->readMiscReg(IPR_IPLR), ipl, summary); -- cgit v1.2.3 From e08cf8fee0a2732aab1d4c6d0ba152282aad9714 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 1 Mar 2006 01:23:10 -0500 Subject: Changed the name of the fault's invocation method from ev5_trap to invoke. --HG-- extra : convert_revision : b7ab14ac644f6a38c69aaa5372b3002b21f34af0 --- cpu/simple/cpu.cc | 4 ++-- cpu/simple/cpu.hh | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index e5c2e18cf..85a3c19ac 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -687,7 +687,7 @@ SimpleCPU::tick() if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) { xc->setMiscReg(IPR_ISR, summary); xc->setMiscReg(IPR_INTID, ipl); - Fault(new InterruptFault)->ev5_trap(xc); + Fault(new InterruptFault)->invoke(xc); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", xc->readMiscReg(IPR_IPLR), ipl, summary); @@ -811,7 +811,7 @@ SimpleCPU::tick() if (fault != NoFault) { #if FULL_SYSTEM - fault->ev5_trap(xc); + fault->invoke(xc); #else // !FULL_SYSTEM fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc); #endif // FULL_SYSTEM diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index 243172821..8396937a8 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -347,7 +347,7 @@ class SimpleCPU : public BaseCPU int readIntrFlag() { return xc->readIntrFlag(); } void setIntrFlag(int val) { xc->setIntrFlag(val); } bool inPalMode() { return xc->inPalMode(); } - void ev5_trap(Fault fault) { fault->ev5_trap(xc); } + void ev5_trap(Fault fault) { fault->invoke(xc); } bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } #else void syscall() { xc->syscall(); } -- cgit v1.2.3 From 2eff368dd03c93a503e13ab82cf4c4abb0c06aa9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 1 Mar 2006 05:26:08 -0500 Subject: Cleaned up some of the Fault system. arch/alpha/ev5.cc: Commented out the intr_post function since it's not used. If this really -is- needed, it should be moved into the fault class. arch/alpha/faults.cc: arch/alpha/faults.hh: Moved the fault invocation code into the fault class fully, and got rid of the need for isA. cpu/exec_context.cc: cpu/exec_context.hh: Removed the trap function from the ExecContext. The faults will execute normally in full system mode, but always panic in syscall emulation mode. cpu/ozone/cpu.hh: cpu/simple/cpu.hh: Changed the execution context executing a fault to a fault executing on the execution context. sim/faults.cc: If not in full system mode, trying to invoke a fault causes a panic. sim/faults.hh: Removed the isA function. --HG-- extra : convert_revision : 894dc8f0755c8efc4b7ef5a09fb2cf7373042395 --- cpu/simple/cpu.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index 8396937a8..0b8d84e53 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -347,7 +347,7 @@ class SimpleCPU : public BaseCPU int readIntrFlag() { return xc->readIntrFlag(); } void setIntrFlag(int val) { xc->setIntrFlag(val); } bool inPalMode() { return xc->inPalMode(); } - void ev5_trap(Fault fault) { fault->invoke(xc); } + void trap(Fault fault) { fault->invoke(xc); } bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } #else void syscall() { xc->syscall(); } -- cgit v1.2.3 From 0fed64a6a47a62a94a53c5f41ac89b34a2fd6786 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 2 Mar 2006 17:49:12 -0500 Subject: Fix fault handling, dereferincing a null pointer is bad. --HG-- extra : convert_revision : a4f658bfd39b7f1d219ad8929b8f45457f49299f --- cpu/simple/cpu.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index d826c589e..ca5d54694 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -347,12 +347,12 @@ SimpleCPU::copySrcTranslate(Addr src) // translate to physical address Fault fault = xc->translateDataReadReq(memReq); - assert(!fault->isAlignmentFault()); - if (fault == NoFault) { xc->copySrcAddr = src; xc->copySrcPhysAddr = memReq->paddr + offset; } else { + assert(!fault->isAlignmentFault()); + xc->copySrcAddr = 0; xc->copySrcPhysAddr = 0; } @@ -382,8 +382,6 @@ SimpleCPU::copy(Addr dest) // translate to physical address Fault fault = xc->translateDataWriteReq(memReq); - assert(!fault->isAlignmentFault()); - if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; // Need to read straight from memory since we have more than 8 bytes. @@ -402,6 +400,9 @@ SimpleCPU::copy(Addr dest) dcacheInterface->access(memReq); } } + else + assert(!fault->isAlignmentFault()); + return fault; } -- cgit v1.2.3 From e7825aab59e03b9691d361338fba222f56446f77 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 3 Mar 2006 15:28:25 -0500 Subject: Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included. The shadow registers are folded into the normal integer registers to ease renaming indexing. Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode. arch/alpha/ev5.cc: Changes to automatically map the shadow registers if the instruction is in PAL mode. arch/alpha/isa/branch.isa: arch/alpha/isa/decoder.isa: arch/alpha/isa/fp.isa: arch/alpha/isa/int.isa: arch/alpha/isa/mem.isa: arch/alpha/isa/pal.isa: arch/alpha/isa/unimp.isa: Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits. arch/alpha/isa/main.isa: Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits. The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode. If it is, then it refers to the reg_redir table to determine the true index of the register it is using. Also include the opcdec instruction definition. arch/alpha/isa_traits.hh: Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not. Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers). Change the dependence tags to reflect the integer registers include the 8 shadow registers. Define function to make an ExtMachInst. Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU. arch/isa_parser.py: Have static insts decode on the ExtMachInst. base/remote_gdb.cc: Support the automatic remapping of shadow registers. Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices. cpu/o3/regfile.hh: Comment out the pal registers; they are now a part of the integer registers. cpu/simple/cpu.cc: Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin. cpu/static_inst.hh: Change from MachInst to ExtMachInst to support shadow register renaming. --HG-- extra : convert_revision : 1d23eabf735e297068e1917445a6348e9f8c88d5 --- cpu/simple/cpu.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index d826c589e..2006f4fe8 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -761,7 +761,7 @@ SimpleCPU::tick() // decode the instruction inst = gtoh(inst); - curStaticInst = StaticInst::decode(inst); + curStaticInst = StaticInst::decode(makeExtMI(inst, xc->readPC())); traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst, xc->regs.pc); -- cgit v1.2.3 From f15e492375e8ecd42a1f0ba7ead68cfeb2b4b673 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sat, 4 Mar 2006 15:18:40 -0500 Subject: Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. The major change is renaming the old ExecContext to CPUExecContext, and creating two new classes, ExecContext (an abstract class), and ProxyExecContext (a templated class that derives from ExecContext). Code outside of the CPU continues to use ExecContext as normal (other than not being able to access variables within the XC). The CPU uses the CPUExecContext, or however else it stores its own state. It then creates a ProxyExecContext, templated on the class used to hold its state. This proxy is passed to any code outside of the CPU that needs to access the XC. This allows code outside of the CPU to use the ExecContext interface to access any state needed, without knowledge of how that state is laid out. Note that these changes will not compile without the accompanying revision to automatically rename the shadow registers. SConscript: Include new file, cpu_exec_context.cc. arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_memory.cc: arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: arch/alpha/isa/decoder.isa: arch/alpha/stacktrace.cc: arch/alpha/vtophys.cc: base/remote_gdb.cc: cpu/intr_control.cc: Avoid directly accessing objects within the XC. arch/alpha/ev5.cc: Avoid directly accessing objects within the XC. KernelStats have been moved to the BaseCPU instead of the XC. arch/alpha/isa_traits.hh: Remove clearIprs(). It wasn't used very often and it did not work well with the proxy ExecContext. cpu/base.cc: Place kernel stats within the BaseCPU instead of the ExecContext. For now comment out the profiling code sampling until its exact location is decided upon. cpu/base.hh: Kernel stats are now in the BaseCPU instead of the ExecContext. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. cpu/exetrace.cc: Remove unneeded include of exec_context.hh. cpu/intr_control.hh: cpu/o3/alpha_cpu_builder.cc: Remove unneeded include of exec_context.hh cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. Also avoid accessing anything directly from the XC. cpu/pc_event.cc: Avoid accessing objects directly from the XC. dev/tsunami_cchip.cc: Avoid accessing objects directly within the XC> kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/linux/linux_threadinfo.hh: kern/tru64/dump_mbuf.cc: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: sim/syscall_emul.cc: sim/syscall_emul.hh: Avoid accessing objects directly within the XC. kern/kernel_stats.cc: kern/kernel_stats.hh: Kernel stats no longer exist within the XC. kern/system_events.cc: Avoid accessing objects directly within the XC. Also kernel stats are now in the BaseCPU. sim/process.cc: sim/process.hh: Avoid accessing regs directly within an ExecContext. Instead use a CPUExecContext to initialize the registers and copy them over. cpu/cpu_exec_context.cc: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. cpu/cpu_exec_context.hh: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. Remove kernel stats from the ExecContext. sim/pseudo_inst.cc: Kernel stats now live within the CPU. Avoid accessing objects directly within the XC. --HG-- rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : a75393a8945c80cca225b5e9d9c22a16609efb85 --- cpu/simple/cpu.cc | 136 ++++++++++++++++++++++++++++-------------------------- cpu/simple/cpu.hh | 53 +++++++++++---------- 2 files changed, 98 insertions(+), 91 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index dd2d53c17..7c60b242f 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -44,6 +44,7 @@ #include "base/stats/events.hh" #include "base/trace.hh" #include "cpu/base.hh" +#include "cpu/cpu_exec_context.hh" #include "cpu/exec_context.hh" #include "cpu/exetrace.hh" #include "cpu/profile.hh" @@ -94,7 +95,7 @@ SimpleCPU::init() ExecContext *xc = execContexts[i]; // initialize CPU, including PC - TheISA::initCPU(&xc->regs, xc->cpu_id); + TheISA::initCPU(xc, xc->readCpuId()); } #endif } @@ -132,22 +133,24 @@ SimpleCPU::CacheCompletionEvent::description() } SimpleCPU::SimpleCPU(Params *p) - : BaseCPU(p), tickEvent(this, p->width), xc(NULL), + : BaseCPU(p), tickEvent(this, p->width), cpuXC(NULL), cacheCompletionEvent(this) { _status = Idle; #if FULL_SYSTEM - xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); + cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); #else - xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0); + cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, + /* asid */ 0); #endif // !FULL_SYSTEM + xcProxy = cpuXC->getProxy(); icacheInterface = p->icache_interface; dcacheInterface = p->dcache_interface; memReq = new MemReq(); - memReq->xc = xc; + memReq->xc = xcProxy; memReq->asid = 0; memReq->data = new uint8_t[64]; @@ -158,7 +161,7 @@ SimpleCPU::SimpleCPU(Params *p) lastIcacheStall = 0; lastDcacheStall = 0; - execContexts.push_back(xc); + execContexts.push_back(xcProxy); } SimpleCPU::~SimpleCPU() @@ -207,7 +210,7 @@ void SimpleCPU::activateContext(int thread_num, int delay) { assert(thread_num == 0); - assert(xc); + assert(cpuXC); assert(_status == Idle); notIdleFraction++; @@ -220,7 +223,7 @@ void SimpleCPU::suspendContext(int thread_num) { assert(thread_num == 0); - assert(xc); + assert(cpuXC); assert(_status == Running); notIdleFraction--; @@ -301,7 +304,7 @@ SimpleCPU::serialize(ostream &os) SERIALIZE_ENUM(_status); SERIALIZE_SCALAR(inst); nameOut(os, csprintf("%s.xc", name())); - xc->serialize(os); + cpuXC->serialize(os); nameOut(os, csprintf("%s.tickEvent", name())); tickEvent.serialize(os); nameOut(os, csprintf("%s.cacheCompletionEvent", name())); @@ -314,7 +317,7 @@ SimpleCPU::unserialize(Checkpoint *cp, const string §ion) BaseCPU::unserialize(cp, section); UNSERIALIZE_ENUM(_status); UNSERIALIZE_SCALAR(inst); - xc->unserialize(cp, csprintf("%s.xc", section)); + cpuXC->unserialize(cp, csprintf("%s.xc", section)); tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); cacheCompletionEvent .unserialize(cp, csprintf("%s.cacheCompletionEvent", section)); @@ -345,16 +348,16 @@ SimpleCPU::copySrcTranslate(Addr src) memReq->reset(src & ~(blk_size - 1), blk_size); // translate to physical address - Fault fault = xc->translateDataReadReq(memReq); + Fault fault = cpuXC->translateDataReadReq(memReq); assert(fault != AlignmentFault); if (fault == NoFault) { - xc->copySrcAddr = src; - xc->copySrcPhysAddr = memReq->paddr + offset; + cpuXC->copySrcAddr = src; + cpuXC->copySrcPhysAddr = memReq->paddr + offset; } else { - xc->copySrcAddr = 0; - xc->copySrcPhysAddr = 0; + cpuXC->copySrcAddr = 0; + cpuXC->copySrcPhysAddr = 0; } return fault; } @@ -367,7 +370,7 @@ SimpleCPU::copy(Addr dest) // Only support block sizes of 64 atm. assert(blk_size == 64); uint8_t data[blk_size]; - //assert(xc->copySrcAddr); + //assert(cpuXC->copySrcAddr); int offset = dest & (blk_size - 1); // Make sure block doesn't span page @@ -380,21 +383,21 @@ SimpleCPU::copy(Addr dest) memReq->reset(dest & ~(blk_size -1), blk_size); // translate to physical address - Fault fault = xc->translateDataWriteReq(memReq); + Fault fault = cpuXC->translateDataWriteReq(memReq); assert(fault != AlignmentFault); if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; // Need to read straight from memory since we have more than 8 bytes. - memReq->paddr = xc->copySrcPhysAddr; - xc->mem->read(memReq, data); + memReq->paddr = cpuXC->copySrcPhysAddr; + cpuXC->mem->read(memReq, data); memReq->paddr = dest_addr; - xc->mem->write(memReq, data); + cpuXC->mem->write(memReq, data); if (dcacheInterface) { memReq->cmd = Copy; memReq->completionEvent = NULL; - memReq->paddr = xc->copySrcPhysAddr; + memReq->paddr = cpuXC->copySrcPhysAddr; memReq->dest = dest_addr; memReq->size = 64; memReq->time = curTick; @@ -411,7 +414,7 @@ Fault SimpleCPU::read(Addr addr, T &data, unsigned flags) { if (status() == DcacheMissStall || status() == DcacheMissSwitch) { - Fault fault = xc->read(memReq,data); + Fault fault = cpuXC->read(memReq,data); if (traceData) { traceData->setAddr(addr); @@ -422,7 +425,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault fault = xc->translateDataReadReq(memReq); + Fault fault = cpuXC->translateDataReadReq(memReq); // if we have a cache, do cache access too if (fault == NoFault && dcacheInterface) { @@ -442,12 +445,12 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) _status = DcacheMissStall; } else { // do functional access - fault = xc->read(memReq, data); + fault = cpuXC->read(memReq, data); } } else if(fault == NoFault) { // do functional access - fault = xc->read(memReq, data); + fault = cpuXC->read(memReq, data); } @@ -507,11 +510,11 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault fault = xc->translateDataWriteReq(memReq); + Fault fault = cpuXC->translateDataWriteReq(memReq); // do functional access if (fault == NoFault) - fault = xc->write(memReq, data); + fault = cpuXC->write(memReq, data); if (fault == NoFault && dcacheInterface) { memReq->cmd = Write; @@ -588,7 +591,7 @@ SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) Addr SimpleCPU::dbg_vtophys(Addr addr) { - return vtophys(xc, addr); + return vtophys(xcProxy, addr); } #endif // FULL_SYSTEM @@ -636,9 +639,9 @@ SimpleCPU::post_interrupt(int int_num, int index) { BaseCPU::post_interrupt(int_num, index); - if (xc->status() == ExecContext::Suspended) { + if (cpuXC->status() == ExecContext::Suspended) { DPRINTF(IPI,"Suspended Processor awoke\n"); - xc->activate(); + cpuXC->activate(); } } #endif // FULL_SYSTEM @@ -654,16 +657,16 @@ SimpleCPU::tick() Fault fault = NoFault; #if FULL_SYSTEM - if (checkInterrupts && check_interrupts() && !xc->inPalMode() && + if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() && status() != IcacheMissComplete) { int ipl = 0; int summary = 0; checkInterrupts = false; - if (xc->readMiscReg(IPR_SIRR)) { + if (cpuXC->readMiscReg(IPR_SIRR)) { for (int i = INTLEVEL_SOFTWARE_MIN; i < INTLEVEL_SOFTWARE_MAX; i++) { - if (xc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { + if (cpuXC->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { // See table 4-19 of 21164 hardware reference ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); @@ -671,7 +674,7 @@ SimpleCPU::tick() } } - uint64_t interrupts = xc->cpu->intr_status(); + uint64_t interrupts = cpuXC->cpu->intr_status(); for (int i = INTLEVEL_EXTERNAL_MIN; i < INTLEVEL_EXTERNAL_MAX; i++) { if (interrupts & (ULL(1) << i)) { @@ -681,24 +684,24 @@ SimpleCPU::tick() } } - if (xc->readMiscReg(IPR_ASTRR)) + if (cpuXC->readMiscReg(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); - if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) { - xc->setMiscReg(IPR_ISR, summary); - xc->setMiscReg(IPR_INTID, ipl); - xc->ev5_trap(InterruptFault); + if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) { + cpuXC->setMiscReg(IPR_ISR, summary); + cpuXC->setMiscReg(IPR_INTID, ipl); + cpuXC->ev5_trap(InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - xc->readMiscReg(IPR_IPLR), ipl, summary); + cpuXC->readMiscReg(IPR_IPLR), ipl, summary); } } #endif // maintain $r0 semantics - xc->regs.intRegFile[ZeroReg] = 0; + cpuXC->setIntReg(ZeroReg, 0); #ifdef TARGET_ALPHA - xc->regs.floatRegFile.d[ZeroReg] = 0.0; + cpuXC->setFloatRegDouble(ZeroReg, 0.0); #endif // TARGET_ALPHA if (status() == IcacheMissComplete) { @@ -720,13 +723,13 @@ SimpleCPU::tick() #endif memReq->cmd = Read; - memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t), - IFETCH_FLAGS(xc->regs.pc)); + memReq->reset(cpuXC->readPC() & ~3, sizeof(uint32_t), + IFETCH_FLAGS(cpuXC->readPC())); - fault = xc->translateInstReq(memReq); + fault = cpuXC->translateInstReq(memReq); if (fault == NoFault) - fault = xc->mem->read(memReq, inst); + fault = cpuXC->mem->read(memReq, inst); if (icacheInterface && fault == NoFault) { memReq->completionEvent = NULL; @@ -763,29 +766,30 @@ SimpleCPU::tick() inst = gtoh(inst); curStaticInst = StaticInst::decode(inst); - traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst, - xc->regs.pc); + traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst, + cpuXC->readPC()); #if FULL_SYSTEM - xc->setInst(inst); + cpuXC->setInst(inst); #endif // FULL_SYSTEM - xc->func_exe_inst++; + cpuXC->func_exe_inst++; fault = curStaticInst->execute(this, traceData); #if FULL_SYSTEM - if (xc->fnbin) { - assert(xc->kernelStats); - system->kernelBinning->execute(xc, inst); + if (system->kernelBinning->fnbin) { + assert(kernelStats); + system->kernelBinning->execute(xcProxy, inst); } - if (xc->profile) { - bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; - xc->profilePC = usermode ? 1 : xc->regs.pc; - ProfileNode *node = xc->profile->consume(xc, inst); + if (cpuXC->profile) { + bool usermode = + (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + cpuXC->profilePC = usermode ? 1 : cpuXC->readPC(); + ProfileNode *node = cpuXC->profile->consume(xcProxy, inst); if (node) - xc->profileNode = node; + cpuXC->profileNode = node; } #endif @@ -805,29 +809,29 @@ SimpleCPU::tick() traceData->finalize(); } - traceFunctions(xc->regs.pc); + traceFunctions(cpuXC->readPC()); } // if (fault == NoFault) if (fault != NoFault) { #if FULL_SYSTEM - xc->ev5_trap(fault); + cpuXC->ev5_trap(fault); #else // !FULL_SYSTEM - fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc); + fatal("fault (%d) detected @ PC 0x%08p", fault, cpuXC->readPC()); #endif // FULL_SYSTEM } else { // go to the next instruction - xc->regs.pc = xc->regs.npc; - xc->regs.npc += sizeof(MachInst); + cpuXC->setPC(cpuXC->readNextPC()); + cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst)); } #if FULL_SYSTEM Addr oldpc; do { - oldpc = xc->regs.pc; - system->pcEventQueue.service(xc); - } while (oldpc != xc->regs.pc); + oldpc = cpuXC->readPC(); + system->pcEventQueue.service(xcProxy); + } while (oldpc != cpuXC->readPC()); #endif assert(status() == Running || diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index 3bc905be1..1441a8fcd 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -32,7 +32,7 @@ #include "base/statistics.hh" #include "config/full_system.hh" #include "cpu/base.hh" -#include "cpu/exec_context.hh" +#include "cpu/cpu_exec_context.hh" #include "cpu/pc_event.hh" #include "cpu/sampler/sampler.hh" #include "cpu/static_inst.hh" @@ -54,6 +54,7 @@ class Process; #endif // FULL_SYSTEM +class ExecContext; class MemInterface; class Checkpoint; @@ -148,7 +149,9 @@ class SimpleCPU : public BaseCPU public: // execution context - ExecContext *xc; + CPUExecContext *cpuXC; + + ExecContext *xcProxy; void switchOut(Sampler *s); void takeOverFrom(BaseCPU *oldCPU); @@ -275,86 +278,86 @@ class SimpleCPU : public BaseCPU uint64_t readIntReg(const StaticInst *si, int idx) { - return xc->readIntReg(si->srcRegIdx(idx)); + return cpuXC->readIntReg(si->srcRegIdx(idx)); } float readFloatRegSingle(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; - return xc->readFloatRegSingle(reg_idx); + return cpuXC->readFloatRegSingle(reg_idx); } double readFloatRegDouble(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; - return xc->readFloatRegDouble(reg_idx); + return cpuXC->readFloatRegDouble(reg_idx); } uint64_t readFloatRegInt(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; - return xc->readFloatRegInt(reg_idx); + return cpuXC->readFloatRegInt(reg_idx); } void setIntReg(const StaticInst *si, int idx, uint64_t val) { - xc->setIntReg(si->destRegIdx(idx), val); + cpuXC->setIntReg(si->destRegIdx(idx), val); } void setFloatRegSingle(const StaticInst *si, int idx, float val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; - xc->setFloatRegSingle(reg_idx, val); + cpuXC->setFloatRegSingle(reg_idx, val); } void setFloatRegDouble(const StaticInst *si, int idx, double val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; - xc->setFloatRegDouble(reg_idx, val); + cpuXC->setFloatRegDouble(reg_idx, val); } void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; - xc->setFloatRegInt(reg_idx, val); + cpuXC->setFloatRegInt(reg_idx, val); } - uint64_t readPC() { return xc->readPC(); } - void setNextPC(uint64_t val) { xc->setNextPC(val); } + uint64_t readPC() { return cpuXC->readPC(); } + void setNextPC(uint64_t val) { cpuXC->setNextPC(val); } MiscReg readMiscReg(int misc_reg) { - return xc->readMiscReg(misc_reg); + return cpuXC->readMiscReg(misc_reg); } MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) { - return xc->readMiscRegWithEffect(misc_reg, fault); + return cpuXC->readMiscRegWithEffect(misc_reg, fault); } Fault setMiscReg(int misc_reg, const MiscReg &val) { - return xc->setMiscReg(misc_reg, val); + return cpuXC->setMiscReg(misc_reg, val); } Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - return xc->setMiscRegWithEffect(misc_reg, val); + return cpuXC->setMiscRegWithEffect(misc_reg, val); } #if FULL_SYSTEM - Fault hwrei() { return xc->hwrei(); } - int readIntrFlag() { return xc->readIntrFlag(); } - void setIntrFlag(int val) { xc->setIntrFlag(val); } - bool inPalMode() { return xc->inPalMode(); } - void ev5_trap(Fault fault) { xc->ev5_trap(fault); } - bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } + Fault hwrei() { return cpuXC->hwrei(); } + int readIntrFlag() { return cpuXC->readIntrFlag(); } + void setIntrFlag(int val) { cpuXC->setIntrFlag(val); } + bool inPalMode() { return cpuXC->inPalMode(); } + void ev5_trap(Fault fault) { cpuXC->ev5_trap(fault); } + bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); } #else - void syscall() { xc->syscall(); } + void syscall() { cpuXC->syscall(); } #endif - bool misspeculating() { return xc->misspeculating(); } - ExecContext *xcBase() { return xc; } + bool misspeculating() { return cpuXC->misspeculating(); } + ExecContext *xcBase() { return xcProxy; } }; #endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ -- cgit v1.2.3 From 11aead894d4186916b587b1449075f276319a235 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 7 Mar 2006 19:59:12 -0500 Subject: Updates for the quiesceEvent that was added to the XC. Also several files need to include system.hh or symtab.hh. This is because exec_context.hh has less #includes than before, requiring some of the files that include it to include some other files as well. arch/alpha/faults.cc: Avoid accessing XC directly. arch/alpha/stacktrace.cc: StackTrace needs to include system.hh. cpu/cpu_exec_context.cc: Update for change to CPUExecContext. cpu/cpu_exec_context.hh: Make quiesce events use CPUExecContext instead of ExecContext. Include functions to allow the quiesce event and last activate/suspend be accessed. cpu/exec_context.hh: Include functions for quiesceEvent. cpu/intr_control.cc: Needs to include cpu/exec_context.hh. cpu/profile.cc: Needs to include symtab.hh for the symbol table. cpu/profile.hh: Needs forward declare of ExecContext. cpu/simple/cpu.cc: Rename xc to cpuXC. dev/tsunami_cchip.cc: Needs to include exec_context.hh. kern/kernel_stats.cc: Needs to include system.hh. kern/linux/events.cc: Needs to include system.hh. Also avoid accessing objects directly from the XC. kern/tru64/dump_mbuf.cc: Include symtab.hh for the SymbolTable and system.hh. kern/tru64/tru64_events.cc: Include system.hh sim/pseudo_inst.cc: Avoid accessing objects directly within the XC. --HG-- extra : convert_revision : 78fe30d98cd20f7403fa216f772071458b675c84 --- cpu/simple/cpu.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 38b43fef5..fd0163677 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -766,7 +766,7 @@ SimpleCPU::tick() // decode the instruction inst = gtoh(inst); - curStaticInst = StaticInst::decode(makeExtMI(inst, xc->readPC())); + curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC())); traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst, cpuXC->readPC()); -- cgit v1.2.3 From a3aae21d031c93ab1b9a90d435d9590dad2482c4 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Thu, 9 Mar 2006 03:27:51 -0500 Subject: last changes before big merge arch/alpha/isa_traits.hh: arch/sparc/isa_traits.hh: add nnpc for compiling purposes in exec_context setNextNPC function cpu/exec_context.hh: set NNPC function cpu/simple/cpu.cc: use NNPC in determining what PC we are using --HG-- extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532 --- cpu/simple/cpu.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 51d679a63..f1a3ebd0b 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -818,9 +818,17 @@ SimpleCPU::tick() #endif // FULL_SYSTEM } else { +#if THE_ISA != MIPS_ISA // go to the next instruction xc->regs.pc = xc->regs.npc; xc->regs.npc += sizeof(MachInst); +#else + // go to the next instruction + xc->regs.pc = xc->regs.npc; + xc->regs.npc = xc->regs.nnpc; + xc->regs.nnpc += sizeof(MachInst); +#endif + } #if FULL_SYSTEM -- cgit v1.2.3 From e30bce8f8e4fdb3dbf4f8161f496c94c85d3d8cf Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 9 Mar 2006 15:10:55 -0500 Subject: Use functions to access XC. cpu/exec_context.hh: Include readNextNPC function. cpu/simple/cpu.cc: Use functions to set and access nextPC, nextNPC. --HG-- extra : convert_revision : 22622b9c110e1d99cc9106a2a27c479579d7e1ad --- cpu/simple/cpu.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu/simple') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index f1a3ebd0b..c85154521 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -825,8 +825,8 @@ SimpleCPU::tick() #else // go to the next instruction xc->regs.pc = xc->regs.npc; - xc->regs.npc = xc->regs.nnpc; - xc->regs.nnpc += sizeof(MachInst); + xc->setNextPC(xc->readNextNPC()); + xc->setNextNPC(xc->readNextNPC() + sizeof(MachInst)); #endif } -- cgit v1.2.3