From 54b47bc5ae7993558412de6c458727171b630594 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Wed, 22 Feb 2006 03:33:35 -0500 Subject: MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!! arch/mips/faults.hh: remove nonsense arch/mips/isa/base.isa: define R31 arch/mips/isa/bitfields.isa: forgotten bitfields arch/mips/isa/decoder.isa: INT64 -> int64_t arch/mips/isa/formats.isa: fix comments arch/mips/isa/formats/branch.isa: Branch -> BranchLikely RB -> RT arch/mips/isa/formats/fp.isa: Make FP ops generates arch/mips/isa/formats/mem.isa: RA,RB -> RS,RT arch/mips/isa/formats/noop.isa: Rc -> Rd arch/mips/isa/formats/util.isa: forgot brace and semicolon arch/mips/isa/includes.isa: remove unnecessary files arch/mips/isa_traits.hh: spacing cpu/static_inst.hh: add cond_delay_slot flag --HG-- extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37 --- cpu/static_inst.hh | 2 ++ 1 file changed, 2 insertions(+) (limited to 'cpu/static_inst.hh') diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index 5106dcf06..db9e73714 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -109,6 +109,8 @@ class StaticInstBase : public RefCounted IsCall, ///< Subroutine call. IsReturn, ///< Subroutine return. + IsCondDelaySlot,///< Conditional Delay-Slot Instruction + IsThreadSync, ///< Thread synchronization operation. IsSerializing, ///< Serializes pipeline: won't execute until all -- cgit v1.2.3