From bd175809286e8da64176da977aeb27fc6ff6d272 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Sat, 18 Feb 2006 14:38:23 -0500 Subject: changes from mergedmem arch/mips/isa/formats/branch.isa: add branch_likely member functions cpu/base.hh: cpu/exec_context.hh: cpu/static_inst.hh: change from mergedmem --HG-- extra : convert_revision : d6ad6943e2ef09eac91a466fc5c9bd8e66bf319a --- cpu/static_inst.hh | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'cpu/static_inst.hh') diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index 24997eadc..c574173c2 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -36,7 +36,7 @@ #include "base/refcnt.hh" #include "encumbered/cpu/full/op_class.hh" #include "sim/host.hh" -#include "arch/isa_traits.hh" +#include "targetarch/isa_traits.hh" // forward declarations struct AlphaSimpleImpl; @@ -113,6 +113,8 @@ class StaticInstBase : public RefCounted IsSerializing, ///< Serializes pipeline: won't execute until all /// older instructions have committed. + IsSerializeBefore, + IsSerializeAfter, IsMemBarrier, ///< Is a memory barrier IsWriteBarrier, ///< Is a write barrier @@ -196,7 +198,11 @@ class StaticInstBase : public RefCounted bool isUncondCtrl() const { return flags[IsUncondControl]; } bool isThreadSync() const { return flags[IsThreadSync]; } - bool isSerializing() const { return flags[IsSerializing]; } + bool isSerializing() const { return flags[IsSerializing] || + flags[IsSerializeBefore] || + flags[IsSerializeAfter]; } + bool isSerializeBefore() const { return flags[IsSerializeBefore]; } + bool isSerializeAfter() const { return flags[IsSerializeAfter]; } bool isMemBarrier() const { return flags[IsMemBarrier]; } bool isWriteBarrier() const { return flags[IsWriteBarrier]; } bool isNonSpeculative() const { return flags[IsNonSpeculative]; } -- cgit v1.2.3