From c32b4ecac1090cc4885c8d4e529b4ade4686058e Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Wed, 15 Mar 2006 16:26:40 -0500 Subject: infinitesimal small baby steps toward MIPS actually working arch/mips/isa/formats/branch.isa: let user know that we alter r31 in disassembly arch/mips/isa_traits.cc: add copyRegs function ... comment out serialize float code for now arch/mips/isa_traits.hh: make FloatRegFile a class ... change values of architectural regs arch/mips/process.cc: change MIPS to Mips base/loader/elf_object.cc: get global pointer initialized to a value base/loader/elf_object.hh: Add global_ptr to elf_object constructor base/loader/object_file.hh: MIPS to Mips base/traceflags.py: SimpleCPU trace flag cpu/simple/cpu.cc: DPRINTF flags for SimpleCPU cpu/static_inst.hh: Add Decoder functions to static_inst.hh --HG-- extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459 --- cpu/static_inst.hh | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'cpu/static_inst.hh') diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index 764020577..a200e2849 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -391,6 +391,17 @@ class StaticInst : public StaticInstBase /// @retval A pointer to the corresponding StaticInst object. //This is defined as inline below. static StaticInstPtr decode(ExtMachInst mach_inst); + + //MIPS Decoder Debug Functions + int getOpcode() { return (machInst & 0xFC000000) >> 26 ; }//31..26 + int getRs() { return (machInst & 0x03E00000) >> 21; } //25...21 + int getRt() { return (machInst & 0x001F0000) >> 16; } //20...16 + int getRd() { return (machInst & 0x0000F800) >> 11; } //15...11 + int getOpname(){ return (machInst & 0x0000003F); }//5...0 + int getBranch(){ return (machInst & 0x0000FFFF); }//5...0 + int getJump(){ return (machInst & 0x03FFFFFF); }//5...0 + int getHint(){ return (machInst & 0x000007C0) >> 6; } //10...6 + std::string getName() { return mnemonic; } }; typedef RefCountingPtr StaticInstBasePtr; -- cgit v1.2.3