From 89dc94f3bc82b9acf9163d437ab132d74bca42d0 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Fri, 25 Feb 2005 21:44:33 -0500 Subject: Make all StaticInst methods const. StaticInst objects represent a particular binary machine instruction and should be immutable after they are constructed. cpu/simple_cpu/simple_cpu.hh: Make StaticInst parameters const. --HG-- extra : convert_revision : e535fa10c842ce173336323f39d9108c1847f8ba --- cpu/simple_cpu/simple_cpu.hh | 16 ++++++++-------- cpu/static_inst.cc | 2 +- cpu/static_inst.hh | 24 ++++++++++++++---------- 3 files changed, 23 insertions(+), 19 deletions(-) (limited to 'cpu') diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 0283545f4..c802a1c06 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -259,47 +259,47 @@ class SimpleCPU : public BaseCPU // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(StaticInst *si, int idx) + uint64_t readIntReg(const StaticInst *si, int idx) { return xc->readIntReg(si->srcRegIdx(idx)); } - float readFloatRegSingle(StaticInst *si, int idx) + float readFloatRegSingle(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegSingle(reg_idx); } - double readFloatRegDouble(StaticInst *si, int idx) + double readFloatRegDouble(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegDouble(reg_idx); } - uint64_t readFloatRegInt(StaticInst *si, int idx) + uint64_t readFloatRegInt(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return xc->readFloatRegInt(reg_idx); } - void setIntReg(StaticInst *si, int idx, uint64_t val) + void setIntReg(const StaticInst *si, int idx, uint64_t val) { xc->setIntReg(si->destRegIdx(idx), val); } - void setFloatRegSingle(StaticInst *si, int idx, float val) + void setFloatRegSingle(const StaticInst *si, int idx, float val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegSingle(reg_idx, val); } - void setFloatRegDouble(StaticInst *si, int idx, double val) + void setFloatRegDouble(const StaticInst *si, int idx, double val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegDouble(reg_idx, val); } - void setFloatRegInt(StaticInst *si, int idx, uint64_t val) + void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; xc->setFloatRegInt(reg_idx, val); diff --git a/cpu/static_inst.cc b/cpu/static_inst.cc index 7069d89ec..d522dbf5a 100644 --- a/cpu/static_inst.cc +++ b/cpu/static_inst.cc @@ -68,7 +68,7 @@ StaticInst::nullStaticInstPtr; template bool -StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) +StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const { if (isDirectCtrl()) { tgt = branchTarget(pc); diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index c442ada35..75bdcc286 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -285,13 +285,13 @@ class StaticInst : public StaticInstBase * String representation of disassembly (lazily evaluated via * disassemble()). */ - std::string *cachedDisassembly; + mutable std::string *cachedDisassembly; /** * Internal function to generate disassembly string. */ - virtual std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) = 0; + virtual std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; /// Constructor. StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass) @@ -311,23 +311,27 @@ class StaticInst : public StaticInstBase /** * Execute this instruction under SimpleCPU model. */ - virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0; + virtual Fault execute(SimpleCPU *xc, + Trace::InstRecord *traceData) const = 0; - /** + /** * Execute this instruction under InorderCPU model. */ - virtual Fault execute(InorderCPU *xc, Trace::InstRecord *traceData) = 0; + virtual Fault execute(InorderCPU *xc, + Trace::InstRecord *traceData) const = 0; /** * Execute this instruction under FastCPU model. */ - virtual Fault execute(FastCPU *xc, Trace::InstRecord *traceData) = 0; + virtual Fault execute(FastCPU *xc, + Trace::InstRecord *traceData) const = 0; /** * Execute this instruction under detailed FullCPU model. */ - virtual Fault execute(DynInst *xc, Trace::InstRecord *traceData) = 0; + virtual Fault execute(DynInst *xc, + Trace::InstRecord *traceData) const = 0; /** * Return the target address for a PC-relative branch. @@ -357,7 +361,7 @@ class StaticInst : public StaticInstBase * Return true if the instruction is a control transfer, and if so, * return the target address as well. */ - bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt); + bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const; /** * Return string representation of disassembled instruction. @@ -367,7 +371,7 @@ class StaticInst : public StaticInstBase * should not be cached, this function should be overridden directly. */ virtual const std::string &disassemble(Addr pc, - const SymbolTable *symtab = 0) + const SymbolTable *symtab = 0) const { if (!cachedDisassembly) cachedDisassembly = -- cgit v1.2.3 From 58c29640b7f9ab9f4d1724b6f2c432c2146175f2 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 1 Mar 2005 00:39:57 -0500 Subject: Add a new operation class for IPR accesses, and have IPR-accessing instructions use it (instead of IntALU, as before). Default config has a single non-pipelined 3-cycle unit. A bit conservative for the ev6 (some are 1, some are 3). arch/alpha/isa_desc: Make hw_mfpr and hw_mtpr use IprAccessOp op class. cpu/full_cpu/op_class.hh: Add IprAccess. --HG-- extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442 --- cpu/full_cpu/op_class.hh | 1 + 1 file changed, 1 insertion(+) (limited to 'cpu') diff --git a/cpu/full_cpu/op_class.hh b/cpu/full_cpu/op_class.hh index a14ccfaed..8e85e8d8a 100644 --- a/cpu/full_cpu/op_class.hh +++ b/cpu/full_cpu/op_class.hh @@ -51,6 +51,7 @@ enum OpClass { FloatSqrtOp, /* floating point square root */ MemReadOp, /* memory read port */ MemWriteOp, /* memory write port */ + IprAccessOp, /* Internal Processor Register read/write port */ InstPrefetchOp, /* instruction prefetch port (on I-cache) */ Num_OpClasses /* total functional unit classes */ }; -- cgit v1.2.3