From 4328480b5602decbcc7239e1884324ce23eaa3ec Mon Sep 17 00:00:00 2001
From: Nathan Binkert <binkertn@umich.edu>
Date: Wed, 10 Nov 2004 18:37:19 -0500
Subject: Don't use the global check_interrupts variable.  Add a per-cpu
 checkInterrupts variable and use that to determine whether an interrupt can
 occur on a given cycle.

arch/alpha/ev5.cc:
    XC -> CPU (and xc -> CPU) since we're really talking about a CPU here
    Don't use the global check_interrupts variable.  Add a per-cpu
    checkInterrupts variable and use that to determine whether an interrupt
    can occur on a given cycle.

--HG--
extra : convert_revision : be4c0247e5834005c60a45796a222cffd327b64e
---
 cpu/base_cpu.cc              | 7 ++++---
 cpu/base_cpu.hh              | 1 +
 cpu/simple_cpu/simple_cpu.cc | 6 ++----
 3 files changed, 7 insertions(+), 7 deletions(-)

(limited to 'cpu')

diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc
index 7fb8b414f..e4dd744a6 100644
--- a/cpu/base_cpu.cc
+++ b/cpu/base_cpu.cc
@@ -53,8 +53,9 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
                  Counter max_loads_any_thread,
                  Counter max_loads_all_threads,
                  System *_system, Tick freq)
-    : SimObject(_name), frequency(freq), deferRegistration(_def_reg),
-      number_of_threads(_number_of_threads), system(_system)
+    : SimObject(_name), frequency(freq), checkInterrupts(true),
+      deferRegistration(_def_reg), number_of_threads(_number_of_threads),
+      system(_system)
 #else
 BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
                  Counter max_insts_any_thread,
@@ -219,7 +220,7 @@ BaseCPU::post_interrupt(int int_num, int index)
     if (index < 0 || index >= sizeof(uint64_t) * 8)
         panic("int_num out of bounds\n");
 
-    AlphaISA::check_interrupts = 1;
+    checkInterrupts = true;
     interrupts[int_num] |= 1 << index;
     intstatus |= (ULL(1) << int_num);
 }
diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh
index 7e937c755..8668c3216 100644
--- a/cpu/base_cpu.hh
+++ b/cpu/base_cpu.hh
@@ -55,6 +55,7 @@ class BaseCPU : public SimObject
     virtual void post_interrupt(int int_num, int index);
     virtual void clear_interrupt(int int_num, int index);
     virtual void clear_interrupts();
+    bool checkInterrupts;
 
     bool check_interrupt(int int_num) const {
         if (int_num > NumInterruptLevels)
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 6af67eee0..04783574f 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -641,13 +641,11 @@ SimpleCPU::tick()
     Fault fault = No_Fault;
 
 #ifdef FULL_SYSTEM
-    if (AlphaISA::check_interrupts &&
-        xc->cpu->check_interrupts() &&
-        !PC_PAL(xc->regs.pc) &&
+    if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
         status() != IcacheMissComplete) {
         int ipl = 0;
         int summary = 0;
-        AlphaISA::check_interrupts = 0;
+        checkInterrupts = false;
         IntReg *ipr = xc->regs.ipr;
 
         if (xc->regs.ipr[TheISA::IPR_SIRR]) {
-- 
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