From 44ef49bd2b66799add0077ecf60c2a111d9a2844 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <binkertn@umich.edu>
Date: Thu, 18 Nov 2004 00:24:36 -0500
Subject: undo simple CPU changes

--HG--
extra : convert_revision : dce0d9f7d34243899f699488c6534fb1ccea4849
---
 cpu/simple_cpu/simple_cpu.cc | 49 +++++++++++---------------------------------
 cpu/simple_cpu/simple_cpu.hh |  6 +-----
 2 files changed, 13 insertions(+), 42 deletions(-)

(limited to 'cpu')

diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 4bd7ce638..d48f93663 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -103,7 +103,7 @@ SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
 
 void SimpleCPU::CacheCompletionEvent::process()
 {
-    cpu->processCacheCompletion(read);
+    cpu->processCacheCompletion();
 }
 
 const char *
@@ -414,25 +414,21 @@ template <class T>
 Fault
 SimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
-    Fault fault;
+    memReq->reset(addr, sizeof(T), flags);
 
-    if (status() == DcacheMissStall) {
-        //Just do the functional access
+    // translate to physical address
+    Fault fault = xc->translateDataReadReq(memReq);
+
+    // do functional access
+    if (fault == No_Fault)
         fault = xc->read(memReq, data);
 
-        if (traceData) {
-            traceData->setAddr(addr);
-            if (fault == No_Fault)
-                traceData->setData(data);
-        }
-        return fault;
+    if (traceData) {
+        traceData->setAddr(addr);
+        if (fault == No_Fault)
+            traceData->setData(data);
     }
 
-    memReq->reset(addr, sizeof(T), flags);
-
-    // translate to physical address
-    fault = xc->translateDataReadReq(memReq);
-
     // if we have a cache, do cache access too
     if (fault == No_Fault && dcacheInterface) {
         memReq->cmd = Read;
@@ -444,25 +440,11 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
         // a miss.  We really should add first-class support for this
         // at some point.
         if (result != MA_HIT && dcacheInterface->doEvents()) {
-            cacheCompletionEvent.read = true;
             memReq->completionEvent = &cacheCompletionEvent;
-            //May later want to pass the staticinst as well, so it can call
-            //it independantly
             lastDcacheStall = curTick;
             unscheduleTickEvent();
             _status = DcacheMissStall;
         }
-        else {
-            // do functional access
-            if (fault == No_Fault)
-                fault = xc->read(memReq, data);
-
-            if (traceData) {
-                traceData->setAddr(addr);
-                if (fault == No_Fault)
-                    traceData->setData(data);
-            }
-        }
     }
 
     if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
@@ -543,7 +525,6 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         // a miss.  We really should add first-class support for this
         // at some point.
         if (result != MA_HIT && dcacheInterface->doEvents()) {
-            cacheCompletionEvent.read = false;
             memReq->completionEvent = &cacheCompletionEvent;
             lastDcacheStall = curTick;
             unscheduleTickEvent();
@@ -615,7 +596,7 @@ Tick save_cycle = 0;
 
 
 void
-SimpleCPU::processCacheCompletion(bool read)
+SimpleCPU::processCacheCompletion()
 {
     switch (status()) {
       case IcacheMissStall:
@@ -625,9 +606,6 @@ SimpleCPU::processCacheCompletion(bool read)
         break;
       case DcacheMissStall:
         dcacheStallCycles += curTick - lastDcacheStall;
-        if (read) {
-            globalsi->execute(this,traceData);
-        }
         _status = Running;
         scheduleTickEvent(1);
         break;
@@ -751,7 +729,6 @@ SimpleCPU::tick()
             // a miss.  We really should add first-class support for this
             // at some point.
             if (result != MA_HIT && icacheInterface->doEvents()) {
-                cacheCompletionEvent.read = false;
                 memReq->completionEvent = &cacheCompletionEvent;
                 lastIcacheStall = curTick;
                 unscheduleTickEvent();
@@ -776,8 +753,6 @@ SimpleCPU::tick()
     inst = htoa(inst);
         StaticInstPtr<TheISA> si(inst);
 
-        globalsi = si;
-
         traceData = Trace::getInstRecord(curTick, xc, this, si,
                                          xc->regs.pc);
 
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 64e45d35e..341a0da23 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -184,8 +184,6 @@ class SimpleCPU : public BaseCPU
     // Refcounted pointer to the one memory request.
     MemReqPtr memReq;
 
-    StaticInstPtr<TheISA> globalsi;
-
     class CacheCompletionEvent : public Event
     {
       private:
@@ -194,8 +192,6 @@ class SimpleCPU : public BaseCPU
       public:
         CacheCompletionEvent(SimpleCPU *_cpu);
 
-        bool read;
-
         virtual void process();
         virtual const char *description();
     };
@@ -242,7 +238,7 @@ class SimpleCPU : public BaseCPU
     Stats::Scalar<> dcacheStallCycles;
     Counter lastDcacheStall;
 
-    void processCacheCompletion(bool read);
+    void processCacheCompletion();
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
-- 
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