From 838273a196c66f3c6ee834ae865db14f313ef1bc Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 28 Jun 2004 16:49:35 -0400 Subject: fix up the recordEvent stuff to support ignoring events arch/alpha/ev5.cc: cpu/simple_cpu/simple_cpu.cc: update for new event interface base/stats/events.cc: implement the ignore event function which matches sim objects from which to ignore events. Make insert event like insert data and make it able to insert many events in a single transaction with the database. base/stats/events.hh: Make it possible to ignore events sim/sim_object.cc: make recordEvent a member function of SimObject to implement the ignore function easily sim/sim_object.hh: implement the ignore event stuff in the sim object. This is a bit of a hack, but an easy place to put it. --HG-- extra : convert_revision : ba3f25a14ad03662c53fb35514860d69be8cd4f0 --- cpu/simple_cpu/simple_cpu.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index bf4cbfbe2..2c7f78cff 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -406,7 +406,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) } if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) - Stats::recordEvent("Uncached Read"); + recordEvent("Uncached Read"); return fault; } @@ -494,7 +494,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) *res = memReq->result; if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) - Stats::recordEvent("Uncached Write"); + recordEvent("Uncached Write"); return fault; } -- cgit v1.2.3