From 7b07b0877f05cffa93b782a76a15791c1126216a Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 2 Feb 2004 10:47:21 -0800 Subject: Change MemReqPtr parameters to references. This avoids incrementing and decrementing the MemReq reference counters on every call and return. arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: cpu/exec_context.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: dev/alpha_console.cc: dev/alpha_console.hh: Change MemReqPtr parameters to references. --HG-- extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5 --- cpu/exec_context.hh | 18 +++++++++--------- cpu/memtest/memtest.cc | 2 +- cpu/memtest/memtest.hh | 4 ++-- 3 files changed, 12 insertions(+), 12 deletions(-) (limited to 'cpu') diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index f3c4b8015..b49db9720 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -189,17 +189,17 @@ class ExecContext int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); } int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); } - Fault translateInstReq(MemReqPtr req) + Fault translateInstReq(MemReqPtr &req) { return itb->translate(req); } - Fault translateDataReadReq(MemReqPtr req) + Fault translateDataReadReq(MemReqPtr &req) { return dtb->translate(req, false); } - Fault translateDataWriteReq(MemReqPtr req) + Fault translateDataWriteReq(MemReqPtr &req) { return dtb->translate(req, true); } @@ -214,7 +214,7 @@ class ExecContext int getInstAsid() { return asid; } int getDataAsid() { return asid; } - Fault dummyTranslation(MemReqPtr req) + Fault dummyTranslation(MemReqPtr &req) { #if 0 assert((req->vaddr >> 48 & 0xffff) == 0); @@ -225,15 +225,15 @@ class ExecContext req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; return No_Fault; } - Fault translateInstReq(MemReqPtr req) + Fault translateInstReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault translateDataReadReq(MemReqPtr req) + Fault translateDataReadReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault translateDataWriteReq(MemReqPtr req) + Fault translateDataWriteReq(MemReqPtr &req) { return dummyTranslation(req); } @@ -241,7 +241,7 @@ class ExecContext #endif template - Fault read(MemReqPtr req, T& data) + Fault read(MemReqPtr &req, T& data) { #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) if (req->flags & LOCKED) { @@ -254,7 +254,7 @@ class ExecContext } template - Fault write(MemReqPtr req, T& data) + Fault write(MemReqPtr &req, T& data) { #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc index db24bb507..4ec5eed59 100644 --- a/cpu/memtest/memtest.cc +++ b/cpu/memtest/memtest.cc @@ -119,7 +119,7 @@ printData(ostream &os, uint8_t *data, int nbytes) } void -MemTest::completeRequest(MemReqPtr req, uint8_t *data) +MemTest::completeRequest(MemReqPtr &req, uint8_t *data) { switch (req->cmd) { case Read: diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh index 3e7dff968..09f22a177 100644 --- a/cpu/memtest/memtest.hh +++ b/cpu/memtest/memtest.hh @@ -108,7 +108,7 @@ class MemTest : public BaseCPU Statistics::Scalar<> numCopies; // called by MemCompleteEvent::process() - void completeRequest(MemReqPtr req, uint8_t *data); + void completeRequest(MemReqPtr &req, uint8_t *data); friend class MemCompleteEvent; }; @@ -122,7 +122,7 @@ class MemCompleteEvent : public Event public: - MemCompleteEvent(MemReqPtr _req, uint8_t *_data, MemTest *_tester) + MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester) : Event(&mainEventQueue), req(_req), data(_data), tester(_tester) { -- cgit v1.2.3 From 956aff1291990639f8a59a95c6b22e0c17bb8cd8 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 2 Feb 2004 15:45:22 -0800 Subject: More conversions of ref-counted parameters to references: Statistics::NodePtr, StaticInstPtr, ethernet PacketPtr. base/statistics.hh: Change NodePtr parameters to Nodeptr &. cpu/exetrace.hh: Change StaticInstPtr parameters to StaticInstPtr &. dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/ethertap.cc: dev/ethertap.hh: change PacketPtr parameters to PacketPtr &. --HG-- extra : convert_revision : a778efdca33b0ec5beb76cf47db0e9e4728897ee --- cpu/exetrace.hh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh index d05dbe0cd..622ecd729 100644 --- a/cpu/exetrace.hh +++ b/cpu/exetrace.hh @@ -91,8 +91,9 @@ class InstRecord : public Record bool regs_valid; public: - InstRecord(Tick _cycle, BaseCPU *_cpu, StaticInstPtr _staticInst, - Addr _pc, bool spec, unsigned _thread) + InstRecord(Tick _cycle, BaseCPU *_cpu, + const StaticInstPtr &_staticInst, + Addr _pc, bool spec, int _thread) : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc), misspeculating(spec), thread(_thread) { -- cgit v1.2.3 From 548b4a1cb045c6675692e8ed7c6375ebb808c803 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 2 Feb 2004 15:55:35 -0800 Subject: Change "Foo& foo" declarations to "Foo &foo". This primarily to be internally consistent (sometimes we used one, sometimes the other, even within the same line of code!). I picked the latter to be symmetric with "Foo *foo". base/cprintf_formats.hh: base/range.hh: base/refcnt.hh: base/res_list.hh: base/statistics.hh: base/str.hh: cpu/exec_context.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: sim/serialize.cc: sim/serialize.hh: sim/syscall_emul.hh: Change "Foo& foo" declarations to "Foo &foo". --HG-- extra : convert_revision : ca1b0e85a578b539214bda3b8d61ac23792f2e87 --- cpu/exec_context.hh | 4 ++-- cpu/simple_cpu/simple_cpu.cc | 2 +- cpu/simple_cpu/simple_cpu.hh | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index b49db9720..768f2e7d4 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -241,7 +241,7 @@ class ExecContext #endif template - Fault read(MemReqPtr &req, T& data) + Fault read(MemReqPtr &req, T &data) { #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) if (req->flags & LOCKED) { @@ -254,7 +254,7 @@ class ExecContext } template - Fault write(MemReqPtr &req, T& data) + Fault write(MemReqPtr &req, T &data) { #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index 0d5fc4077..e9284ad31 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -321,7 +321,7 @@ change_thread_state(int thread_number, int activate, int priority) // precise architected memory state accessor macros template Fault -SimpleCPU::read(Addr addr, T& data, unsigned flags) +SimpleCPU::read(Addr addr, T &data, unsigned flags) { memReq->reset(addr, sizeof(T), flags); diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 7c9d4ea75..16753fa4f 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -227,7 +227,7 @@ class SimpleCPU : public BaseCPU virtual void unserialize(Checkpoint *cp, const std::string §ion); template - Fault read(Addr addr, T& data, unsigned flags); + Fault read(Addr addr, T &data, unsigned flags); template Fault write(T data, Addr addr, unsigned flags, -- cgit v1.2.3 From b79f6b3273057d99809aced133333552778fd055 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 2 Feb 2004 18:14:11 -0800 Subject: insn->inst --HG-- extra : convert_revision : fcc556fb7e65855ec3c04ef272177c8e7a38fff9 --- cpu/base_cpu.cc | 8 ++++---- cpu/base_cpu.hh | 2 +- cpu/exec_context.cc | 12 ++++++------ cpu/exec_context.hh | 2 +- cpu/simple_cpu/simple_cpu.cc | 8 ++++---- 5 files changed, 16 insertions(+), 16 deletions(-) (limited to 'cpu') diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc index 74d2ceada..604ee335d 100644 --- a/cpu/base_cpu.cc +++ b/cpu/base_cpu.cc @@ -71,16 +71,16 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, maxThreadsPerCPU = number_of_threads; // allocate per-thread instruction-based event queues - comInsnEventQueue = new (EventQueue *)[number_of_threads]; + comInstEventQueue = new (EventQueue *)[number_of_threads]; for (int i = 0; i < number_of_threads; ++i) - comInsnEventQueue[i] = new EventQueue("instruction-based event queue"); + comInstEventQueue[i] = new EventQueue("instruction-based event queue"); // // set up instruction-count-based termination events, if any // if (max_insts_any_thread != 0) for (int i = 0; i < number_of_threads; ++i) - new SimExitEvent(comInsnEventQueue[i], max_insts_any_thread, + new SimExitEvent(comInstEventQueue[i], max_insts_any_thread, "a thread reached the max instruction count"); if (max_insts_all_threads != 0) { @@ -90,7 +90,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, int *counter = new int; *counter = number_of_threads; for (int i = 0; i < number_of_threads; ++i) - new CountedExitEvent(comInsnEventQueue[i], + new CountedExitEvent(comInstEventQueue[i], "all threads reached the max instruction count", max_insts_all_threads, *counter); } diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh index af1f34b67..648035732 100644 --- a/cpu/base_cpu.hh +++ b/cpu/base_cpu.hh @@ -128,7 +128,7 @@ class BaseCPU : public SimObject * scheduling events based on number of instructions committed by * a particular thread. */ - EventQueue **comInsnEventQueue; + EventQueue **comInstEventQueue; /** * Vector of per-thread load-based event queues. Used for diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc index 23ae7eda8..6a5f463cd 100644 --- a/cpu/exec_context.cc +++ b/cpu/exec_context.cc @@ -51,7 +51,7 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, #ifdef FS_MEASURE swCtx(NULL), #endif - func_exe_insn(0), storeCondFailures(0) + func_exe_inst(0), storeCondFailures(0) { memset(®s, 0, sizeof(RegFile)); } @@ -61,14 +61,14 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, : _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num), cpu_id(-1), process(_process), mem(process->getMemory()), asid(_asid), - func_exe_insn(0), storeCondFailures(0) + func_exe_inst(0), storeCondFailures(0) { } ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, int _asid) : cpu(_cpu), thread_num(_thread_num), process(0), mem(_mem), asid(_asid), - func_exe_insn(0), storeCondFailures(0) + func_exe_inst(0), storeCondFailures(0) { } #endif @@ -92,7 +92,7 @@ ExecContext::takeOverFrom(ExecContext *oldContext) #endif regs = oldContext->regs; cpu_id = oldContext->cpu_id; - func_exe_insn = oldContext->func_exe_insn; + func_exe_inst = oldContext->func_exe_inst; storeCondFailures = 0; @@ -106,7 +106,7 @@ ExecContext::serialize(ostream &os) SERIALIZE_ENUM(_status); regs.serialize(os); // thread_num and cpu_id are deterministic from the config - SERIALIZE_SCALAR(func_exe_insn); + SERIALIZE_SCALAR(func_exe_inst); } @@ -116,7 +116,7 @@ ExecContext::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_ENUM(_status); regs.unserialize(cp, section); // thread_num and cpu_id are deterministic from the config - UNSERIALIZE_SCALAR(func_exe_insn); + UNSERIALIZE_SCALAR(func_exe_inst); } diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 768f2e7d4..e9dc5efec 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -158,7 +158,7 @@ class ExecContext * number of executed instructions, for matching with syscall trace * points in EIO files. */ - Counter func_exe_insn; + Counter func_exe_inst; // // Count failed store conditionals so we can warn of apparent diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index e9284ad31..2e4dff280 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -653,7 +653,7 @@ SimpleCPU::tick() numInst++; // check for instruction-count-based events - comInsnEventQueue[0]->serviceEvents(numInst); + comInstEventQueue[0]->serviceEvents(numInst); // decode the instruction StaticInstPtr si(inst); @@ -666,7 +666,7 @@ SimpleCPU::tick() xc->regs.ra = (inst >> 21) & 0x1f; #endif // FULL_SYSTEM - xc->func_exe_insn++; + xc->func_exe_inst++; fault = si->execute(this, xc, traceData); #ifdef FS_MEASURE @@ -770,10 +770,10 @@ END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) INIT_PARAM_DFLT(max_insts_any_thread, - "terminate when any thread reaches this insn count", + "terminate when any thread reaches this inst count", 0), INIT_PARAM_DFLT(max_insts_all_threads, - "terminate when all threads have reached this insn count", + "terminate when all threads have reached this inst count", 0), INIT_PARAM_DFLT(max_loads_any_thread, "terminate when any thread reaches this load count", -- cgit v1.2.3 From 19cc1449609ccd694176d80dff79b92d1402ed14 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 2 Feb 2004 18:58:23 -0800 Subject: Get rid of LVQ-port function unit... only used for redundant multithreading, which has been gone for a long time. --HG-- extra : convert_revision : 717d13455483c3adc7b7cbbcc5f7493d51867974 --- cpu/full_cpu/op_class.hh | 1 - 1 file changed, 1 deletion(-) (limited to 'cpu') diff --git a/cpu/full_cpu/op_class.hh b/cpu/full_cpu/op_class.hh index 67ccaabad..dbaa6624a 100644 --- a/cpu/full_cpu/op_class.hh +++ b/cpu/full_cpu/op_class.hh @@ -51,7 +51,6 @@ enum OpClass { FloatSQRT, /* floating point square root */ RdPort, /* memory read port */ WrPort, /* memory write port */ - LvqPort, /* load value queue read port (redundant threading) */ IPrefPort, Num_OpClasses /* total functional unit classes */ }; -- cgit v1.2.3 From 3e5070a3f121d84846de16718575567725129db9 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 3 Feb 2004 07:19:05 -0800 Subject: Fix bug: forgot branchTarget() method on indirect branches. arch/alpha/isa_desc: Add missing branchTarget() method for indirect branches. cpu/static_inst.hh: Add comment clarifying when branchTarget() can be used on indirect branches. --HG-- extra : convert_revision : 0dcfb36a9792a338cefceb3d1501825abace7ac5 --- cpu/static_inst.hh | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index 644c7dfc4..f3fd6fa24 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -312,10 +312,11 @@ class StaticInst : public StaticInstBase } /** - * Return the target address for an indirect branch (jump). - * The register value is read from the supplied execution context. - * Invalid if not an indirect branch (i.e. isIndirectCtrl() - * should be true). + * Return the target address for an indirect branch (jump). The + * register value is read from the supplied execution context, so + * the result is valid only if the execution context is about to + * execute the branch in question. Invalid if not an indirect + * branch (i.e. isIndirectCtrl() should be true). */ virtual Addr branchTarget(ExecContext *xc) { -- cgit v1.2.3