From aeb8e8ccb7d9a69e44c3943a5e82b6e58e7082f3 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 24 Mar 2004 23:29:10 -0800 Subject: Minor cleanup from building & diffing behavior on various platforms. base/hashmap.hh: gcc on Alpha doesn't always define __LP64__, even though it arguably should. cpu/exec_context.cc: Clear register file on non-full-system too (even though it typically gets overwritten by the initial regs from the Process object). sim/process.cc: Clear initial register copy in Process object. Not all regs get initialized when the executable is loaded. --HG-- extra : convert_revision : f1fe4734a5ea81331d70994cb5284b1e9db0dceb --- cpu/exec_context.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'cpu') diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc index eedd8b8a8..e7d3e0b91 100644 --- a/cpu/exec_context.cc +++ b/cpu/exec_context.cc @@ -60,6 +60,7 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, process(_process), mem(process->getMemory()), asid(_asid), func_exe_inst(0), storeCondFailures(0) { + memset(®s, 0, sizeof(RegFile)); } ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, @@ -67,6 +68,7 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, : cpu(_cpu), thread_num(_thread_num), process(0), mem(_mem), asid(_asid), func_exe_inst(0), storeCondFailures(0) { + memset(®s, 0, sizeof(RegFile)); } #endif -- cgit v1.2.3 From 782fb42992076dfd88ffb7d0c4e689d1bb1220d8 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Fri, 2 Apr 2004 22:57:08 -0800 Subject: Basic cleanup pass to get rid of a few things that made the Python configuration unnecessarily awkward. Biggest changes are: - External and internal object names now match in all cases. The macros still allow them to be different; the only reason I didn't get rid of that is that the macros themselves should be going away soon. In the few conflicting cases, I sometimes renamed the C++ object and sometimes renamed the config object. The latter sets of substitions are: s/BaseBus/Bus/; s/MemoryObject/FunctionalMemory/; s/MemoryControl/MemoryController/; s/FUPool/FuncUnitPool/; - SamplingCPU is temporarily broken... we need to change the model of how this works in the .ini file. Having it as a CPU proxy is really awkward. arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: cpu/simple_cpu/simple_cpu.cc: sim/process.cc: Rename objects to match config name. cpu/base_cpu.cc: Uncomment SimObject define since SamplingCPU no longer does this for us. dev/ethertap.cc: Use unsigned instead of uint16_t for params. kern/tru64/tru64_system.cc: Use unsigned instead of uint64_t for init_param param. test/paramtest.cc: Fix old SimObjectParam. --HG-- extra : convert_revision : 378ebbc6a71ad0694501d09979a44d111a59e8dc --- cpu/base_cpu.cc | 6 ------ cpu/simple_cpu/simple_cpu.cc | 12 ++++-------- 2 files changed, 4 insertions(+), 14 deletions(-) (limited to 'cpu') diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc index 367662f25..e00de8389 100644 --- a/cpu/base_cpu.cc +++ b/cpu/base_cpu.cc @@ -237,10 +237,4 @@ BaseCPU::clear_interrupts() #endif // FULL_SYSTEM -// -// This declaration is not needed now that SamplingCPU provides a -// BaseCPUBuilder object. -// -#if 0 DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) -#endif diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index c2796efd0..711c81c51 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -116,7 +116,7 @@ SimpleCPU::SimpleCPU(const string &_name, Counter max_insts_all_threads, Counter max_loads_any_thread, Counter max_loads_all_threads, - AlphaItb *itb, AlphaDtb *dtb, + AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem, MemInterface *icache_interface, MemInterface *dcache_interface, @@ -778,8 +778,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) Param max_loads_all_threads; #ifdef FULL_SYSTEM - SimObjectParam itb; - SimObjectParam dtb; + SimObjectParam itb; + SimObjectParam dtb; SimObjectParam mem; SimObjectParam system; Param mult; @@ -852,11 +852,7 @@ CREATE_SIM_OBJECT(SimpleCPU) defer_registration); #endif // FULL_SYSTEM -#if 0 - if (!defer_registration) { - cpu->registerExecContexts(); - } -#endif + return cpu; } -- cgit v1.2.3 From 65205b82acee56b0034c0122d5f5a89f57c760fc Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 3 Apr 2004 13:46:10 -0800 Subject: More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL). Also missed renames in a bunch of config files somehow. (See previous changeset for list of renames.) arch/alpha/alpha_memory.cc: arch/alpha/ev5.cc: arch/alpha/faults.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/simple_cpu/simple_cpu.hh: More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL). --HG-- extra : convert_revision : b2c6ca0916b72b59895520fcacaf028667560a0d --- cpu/exec_context.cc | 2 +- cpu/exec_context.hh | 6 +++--- cpu/simple_cpu/simple_cpu.hh | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'cpu') diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc index e7d3e0b91..a89cf4bb5 100644 --- a/cpu/exec_context.cc +++ b/cpu/exec_context.cc @@ -42,7 +42,7 @@ using namespace std; // constructor #ifdef FULL_SYSTEM ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, - AlphaItb *_itb, AlphaDtb *_dtb, + AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_mem) : _status(ExecContext::Unallocated), kernelStats(this, _cpu), cpu(_cpu), thread_num(_thread_num), diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index a72516ac7..f2f2c0879 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -124,8 +124,8 @@ class ExecContext #ifdef FULL_SYSTEM FunctionalMemory *mem; - AlphaItb *itb; - AlphaDtb *dtb; + AlphaITB *itb; + AlphaDTB *dtb; System *system; // the following two fields are redundant, since we can always @@ -174,7 +174,7 @@ class ExecContext // constructor: initialize context from given process structure #ifdef FULL_SYSTEM ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, - AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem); + AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); #else ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 9edd66ab4..d634753b9 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -40,8 +40,8 @@ #ifdef FULL_SYSTEM class Processor; class Kernel; -class AlphaItb; -class AlphaDtb; +class AlphaITB; +class AlphaDTB; class PhysicalMemory; class RemoteGDB; @@ -131,7 +131,7 @@ class SimpleCPU : public BaseCPU System *_system, Counter max_insts_any_thread, Counter max_insts_all_threads, Counter max_loads_any_thread, Counter max_loads_all_threads, - AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem, + AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem, MemInterface *icache_interface, MemInterface *dcache_interface, bool _def_reg, Tick freq); -- cgit v1.2.3 From 25a358983a31167e048b19dd21bc1ec872890a74 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 4 May 2004 17:01:00 -0400 Subject: Major stats package cleanup Add support for generic visitors for stats and use them to implement independent output functions. Support for mysql output and some initial code for hacking on mysql output with python arch/alpha/pseudo_inst.cc: base/hybrid_pred.cc: base/hybrid_pred.hh: base/sat_counter.cc: base/sat_counter.hh: cpu/simple_cpu/simple_cpu.cc: kern/tru64/tru64_events.cc: sim/main.cc: sim/process.cc: sim/process.hh: sim/sim_events.cc: sim/sim_object.cc: sim/system.hh: update for changes in stats package base/statistics.cc: move the python output code to base/stats/puthon.(cc|hh) and reimplement it as a visitor. move the text output code to base/stats/text.(cc|hh) and reimplement it as a visitor. move the database stuff into base/stats/statdb.(cc|hh) and get rid of the class. Put everything as globals in the Statistics::Database namespace. allocate unique ids for all stats. directly implement the check routine and get rid of the various dumping routines since they're now in separate files. make sure that no two stats have the same name clean up some loops base/statistics.hh: major changes to the statistics package again lots of code was factored out of statistics.hh into several separate files in base/stats/ (this will continue) There are now two Stat package types Result and Counter that are specified to allow the user to keep the counted type separate from the result type. They are currently both doubles but that's an experiment. There is no more per stat ability to set the type. Statistics::Counter is not the same as Counter! Implement a visitor for statistics output so that new output types can be implemented independently from the stats package itself. Add a unique id to each stat so that it can be used to keep track of stats more simply. This number can also be used in debugging problems with stats. Tweak the bucket size stuff a bit to make it work better. fixed VectorDist size bug cpu/memtest/memtest.cc: Fix up for changes in stats package Don't use value() since it doesn't work with binning. If you want a number as a stat, and to use it in the program itself, you really want two separate variables, one that's a stat, and one that's not. cpu/memtest/memtest.hh: Fix up for changes in stats package test/Makefile: Try to build stuff now that directories matter test/stattest.cc: test all new output types choose which one with command line options --HG-- extra : convert_revision : e3a3f5f0828c67c0e2de415d936ad240adaddc89 --- cpu/memtest/memtest.cc | 22 ++++++++++++---------- cpu/memtest/memtest.hh | 9 +++++---- cpu/simple_cpu/simple_cpu.cc | 2 +- 3 files changed, 18 insertions(+), 15 deletions(-) (limited to 'cpu') diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc index 051d9623a..5d608976d 100644 --- a/cpu/memtest/memtest.cc +++ b/cpu/memtest/memtest.cc @@ -40,7 +40,7 @@ #include "mem/functional_mem/main_memory.hh" #include "sim/builder.hh" #include "sim/sim_events.hh" -#include "sim/sim_stats.hh" +#include "sim/stats.hh" using namespace std; @@ -109,7 +109,6 @@ MemTest::MemTest(const string &name, // set up counters noResponseCycles = 0; numReads = 0; - numWrites = 0; tickEvent.schedule(0); } @@ -142,21 +141,23 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data) } numReads++; + numReadsStat++; - if (numReads.value() == nextProgressMessage) { - cerr << name() << ": completed " << numReads.value() - << " read accesses @ " << curTick << endl; + if (numReads == nextProgressMessage) { + ccprintf(cerr, "%s: completed %d read accesses @%d\n", + name(), numReads, curTick); nextProgressMessage += progressInterval; } - comLoadEventQueue[0]->serviceEvents(numReads.value()); + comLoadEventQueue[0]->serviceEvents(numReads); break; case Write: - numWrites++; + numWritesStat++; break; case Copy: + numCopiesStat++; break; default: @@ -187,17 +188,18 @@ MemTest::regStats() { using namespace Statistics; - numReads + + numReadsStat .name(name() + ".num_reads") .desc("number of read accesses completed") ; - numWrites + numWritesStat .name(name() + ".num_writes") .desc("number of write accesses completed") ; - numCopies + numCopiesStat .name(name() + ".num_copies") .desc("number of copy accesses completed") ; diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh index da6e180a0..f2409d54c 100644 --- a/cpu/memtest/memtest.hh +++ b/cpu/memtest/memtest.hh @@ -36,7 +36,7 @@ #include "cpu/exec_context.hh" #include "base/statistics.hh" -#include "sim/sim_stats.hh" +#include "sim/stats.hh" class MemTest : public BaseCPU { @@ -110,9 +110,10 @@ class MemTest : public BaseCPU Tick noResponseCycles; - Statistics::Scalar<> numReads; - Statistics::Scalar<> numWrites; - Statistics::Scalar<> numCopies; + uint64_t numReads; + Statistics::Scalar<> numReadsStat; + Statistics::Scalar<> numWritesStat; + Statistics::Scalar<> numCopiesStat; // called by MemCompleteEvent::process() void completeRequest(MemReqPtr &req, uint8_t *data); diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index 711c81c51..f29d9d60e 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -56,7 +56,7 @@ #include "sim/host.hh" #include "sim/sim_events.hh" #include "sim/sim_object.hh" -#include "sim/sim_stats.hh" +#include "sim/stats.hh" #ifdef FULL_SYSTEM #include "base/remote_gdb.hh" -- cgit v1.2.3 From 7cab07268ff6cf1b4ecb59c0e6a377f8bb1ea24a Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 10 May 2004 16:10:47 -0700 Subject: Do a better job of factoring out CPU model in ISA description. (Still not perfect though.) arch/alpha/isa_desc: Do a better job of factoring out CPU model. (Still not perfect though.) Pull execute() methods out of class declarations into separate section of file, allowing (1) easier replication for different CPU models and (2) a path to putting them all in a separate file. Force all instruction execution context into a single model-dependent class (SimpleCPU itself for SimpleCPU, DynInst for FullCPU). arch/isa_parser.py: Do a better job of factoring out CPU model. (Still not perfect though.) Pull execute() methods out of class declarations into separate section of file, allowing (1) easier replication for different CPU models and (2) a path to putting them all in a separate file. Also restructure top level to allow parser to run under interactive interpreter session for easier debugging. cpu/exec_context.hh: Add a few new methods to clean up isa_desc. cpu/simple_cpu/simple_cpu.cc: cpu/static_inst.hh: StaticInst::execute no longer takes a CPU and an ExecContext, just a unified FooCPUExecContext. cpu/simple_cpu/simple_cpu.hh: Add methods to redirect calls to ExecContext so SimpleCPU can act as sole instruction execution context for itself. Typedef SimpleCPU to SimpleCPUExecContext. --HG-- extra : convert_revision : ecc445503bc585585da5663fe61796580e744da6 --- cpu/exec_context.hh | 3 +++ cpu/simple_cpu/simple_cpu.cc | 2 +- cpu/simple_cpu/simple_cpu.hh | 50 ++++++++++++++++++++++++++++++++++++++++++++ cpu/static_inst.hh | 10 ++++----- 4 files changed, 59 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index f2f2c0879..7be83539a 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -387,7 +387,10 @@ class ExecContext #ifdef FULL_SYSTEM uint64_t readIpr(int idx, Fault &fault); Fault setIpr(int idx, uint64_t val); + int readIntrFlag() { return regs.intrflag; } + void setIntrFlag(int val) { regs.intrflag = val; } Fault hwrei(); + bool inPalMode() { return PC_PAL(regs.pc); } void ev5_trap(Fault fault); bool simPalCheck(int palFunc); #endif diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index f29d9d60e..065140883 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -714,7 +714,7 @@ SimpleCPU::tick() xc->func_exe_inst++; - fault = si->execute(this, xc, traceData); + fault = si->execute(this, traceData); #ifdef FULL_SYSTEM SWContext *ctx = xc->swCtx; diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index d634753b9..4977e6992 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -250,6 +250,56 @@ class SimpleCPU : public BaseCPU Fault copySrcTranslate(Addr src); Fault copy(Addr dest); + + uint64_t readIntReg(int reg_idx) { return xc->readIntReg(reg_idx); } + + float readFloatRegSingle(int reg_idx) + { return xc->readFloatRegSingle(reg_idx); } + + double readFloatRegDouble(int reg_idx) + { return xc->readFloatRegDouble(reg_idx); } + + uint64_t readFloatRegInt(int reg_idx) + { return xc->readFloatRegInt(reg_idx); } + + void setIntReg(int reg_idx, uint64_t val) + { return xc->setIntReg(reg_idx, val); } + + void setFloatRegSingle(int reg_idx, float val) + { return xc->setFloatRegSingle(reg_idx, val); } + + void setFloatRegDouble(int reg_idx, double val) + { return xc->setFloatRegDouble(reg_idx, val); } + + void setFloatRegInt(int reg_idx, uint64_t val) + { return xc->setFloatRegInt(reg_idx, val); } + + uint64_t readPC() { return xc->readPC(); } + void setNextPC(uint64_t val) { return xc->setNextPC(val); } + + uint64_t readUniq() { return xc->readUniq(); } + void setUniq(uint64_t val) { return xc->setUniq(val); } + + uint64_t readFpcr() { return xc->readFpcr(); } + void setFpcr(uint64_t val) { return xc->setFpcr(val); } + +#ifdef FULL_SYSTEM + uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); } + Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } + Fault hwrei() { return xc->hwrei(); } + int readIntrFlag() { return xc->readIntrFlag(); } + void setIntrFlag(int val) { xc->setIntrFlag(val); } + bool inPalMode() { return xc->inPalMode(); } + void ev5_trap(Fault fault) { return xc->ev5_trap(fault); } + bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } +#else + void syscall() { xc->syscall(); } +#endif + + bool misspeculating() { return xc->misspeculating(); } + ExecContext *xcBase() { return xc; } }; +typedef SimpleCPU SimpleCPUExecContext; + #endif // __SIMPLE_CPU_HH__ diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index cdf9aefa0..57208f8e6 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -41,10 +41,10 @@ // forward declarations class ExecContext; -class SpecExecContext; -class SimpleCPU; -class FullCPU; class DynInst; +typedef DynInst FullCPUExecContext; +class SimpleCPU; +typedef SimpleCPU SimpleCPUExecContext; class SymbolTable; namespace Trace { @@ -307,13 +307,13 @@ class StaticInst : public StaticInstBase /** * Execute this instruction under SimpleCPU model. */ - virtual Fault execute(SimpleCPU *cpu, ExecContext *xc, + virtual Fault execute(SimpleCPUExecContext *xc, Trace::InstRecord *traceData) = 0; /** * Execute this instruction under detailed FullCPU model. */ - virtual Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, + virtual Fault execute(FullCPUExecContext *xc, Trace::InstRecord *traceData) = 0; /** -- cgit v1.2.3