From b6247c9ea7ddc459a076dddf5e5f330da0211c1e Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Thu, 23 Feb 2006 17:02:34 -0500 Subject: Add support for multiple ports on the memory. Hook up simple cpu to memory. Ready to start testing if I could fix the linking errors I can't ever seem to fix. cpu/simple/cpu.cc: cpu/simple/cpu.hh: Add connecting of ports until builder can handle it. mem/physical.cc: Add function to allocate a port in the object Remove some full_sys stuff untill needed mem/physical.hh: Add function to allocate a port in the object python/m5/objects/BaseCPU.py: Update the params sim/process.cc: Make sure to use the right name (hopefully CPU constructor already called) --HG-- extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85 --- cpu/simple/cpu.cc | 17 ++++++++++++++--- cpu/simple/cpu.hh | 4 ++-- 2 files changed, 16 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index c34cf9079..7da000a35 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -143,6 +143,17 @@ SimpleCPU::SimpleCPU(Params *p) memPort = &dcachePort; + //Create Memory Ports (conect them up) + p->mem->addPort("DCACHE"); + dcachePort.setPeer(p->mem->getPort("DCACHE")); + (p->mem->getPort("DCACHE"))->setPeer(&dcachePort); + + p->mem->addPort("ICACHE"); + icachePort.setPeer(p->mem->getPort("ICACHE")); + (p->mem->getPort("ICACHE"))->setPeer(&icachePort); + + + req = new CpuRequest; req->asid = 0; @@ -1019,11 +1030,11 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) #if FULL_SYSTEM SimObjectParam itb; SimObjectParam dtb; - SimObjectParam mem; SimObjectParam system; Param cpu_id; Param profile; #else + SimObjectParam mem; SimObjectParam workload; #endif // FULL_SYSTEM @@ -1050,11 +1061,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) #if FULL_SYSTEM INIT_PARAM(itb, "Instruction TLB"), INIT_PARAM(dtb, "Data TLB"), - INIT_PARAM(mem, "memory"), INIT_PARAM(system, "system object"), INIT_PARAM(cpu_id, "processor ID"), INIT_PARAM(profile, ""), #else + INIT_PARAM(mem, "memory"), INIT_PARAM(workload, "processes to run"), #endif // FULL_SYSTEM @@ -1085,11 +1096,11 @@ CREATE_SIM_OBJECT(SimpleCPU) #if FULL_SYSTEM params->itb = itb; params->dtb = dtb; - params->mem = mem; params->system = system; params->cpu_id = cpu_id; params->profile = profile; #else + params->mem = mem; params->process = workload; #endif diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index 6df553fe2..3354166cc 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -46,7 +46,7 @@ class Processor; class AlphaITB; class AlphaDTB; -class PhysicalMemory; +class Memory; class RemoteGDB; class GDBListener; @@ -164,8 +164,8 @@ class SimpleCPU : public BaseCPU #if FULL_SYSTEM AlphaITB *itb; AlphaDTB *dtb; - FunctionalMemory *mem; #else + Memory *mem; Process *process; #endif }; -- cgit v1.2.3