From c27c122afc6b778e67a9c77915fac71730a5a4ef Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Sun, 26 Mar 2006 21:44:22 -0500
Subject: Add the bus and connector objects to scons change getPort parameter
 from char* to string Add an extra phase between construction and init called
 connect

SConscript:
    Add the bus and connector objects to scons
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    the connection to memory shouldn't be made until we know the memory
    object exists (e.g. after construction)
dev/io_device.hh:
    change to const string
mem/bus.hh:
    change getPort parameter from char* to string
    initialize num_interfaces
mem/mem_object.hh:
    change getPort parameter from char* to string
mem/physical.cc:
mem/physical.hh:
    change getPort parameter from char* to string
    get rid of the bus object I created last time
python/m5/objects/PhysicalMemory.py:
    get rid of the bus object I created last time
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
    Add an extra phase between construction and init called connect

--HG--
extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
---
 cpu/simple/cpu.cc | 20 ++++++++++----------
 cpu/simple/cpu.hh |  1 +
 2 files changed, 11 insertions(+), 10 deletions(-)

(limited to 'cpu')

diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index d188074d4..8a9e41d53 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -86,6 +86,15 @@ SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
 void
 SimpleCPU::init()
 {
+    //Create Memory Ports (conect them up)
+    Port *mem_dport = mem->getPort("");
+    dcachePort.setPeer(mem_dport);
+    mem_dport->setPeer(&dcachePort);
+
+    Port *mem_iport = mem->getPort("");
+    icachePort.setPeer(mem_iport);
+    mem_iport->setPeer(&icachePort);
+
     BaseCPU::init();
 #if FULL_SYSTEM
     for (int i = 0; i < execContexts.size(); ++i) {
@@ -146,20 +155,11 @@ SimpleCPU::CpuPort::recvRetry()
 }
 
 SimpleCPU::SimpleCPU(Params *p)
-    : BaseCPU(p), icachePort(this),
+    : BaseCPU(p), mem(p->mem), icachePort(this),
       dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
 {
     _status = Idle;
 
-    //Create Memory Ports (conect them up)
-    Port *mem_dport = p->mem->getPort();
-    dcachePort.setPeer(mem_dport);
-    mem_dport->setPeer(&dcachePort);
-
-    Port *mem_iport = p->mem->getPort();
-    icachePort.setPeer(mem_iport);
-    mem_iport->setPeer(&icachePort);
-
 #if FULL_SYSTEM
     cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
 #else
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index dc07027f9..43287a33b 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -105,6 +105,7 @@ class SimpleCPU : public BaseCPU
         virtual Packet *recvRetry();
     };
 
+    MemObject *mem;
     CpuPort icachePort;
     CpuPort dcachePort;
 
-- 
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