From 8f8d09538f58d2e56d7f61b595e64bd06cce8484 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 24 Apr 2006 19:31:50 -0400 Subject: Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e --- dev/alpha_console.cc | 56 +++++++++++++++++++++------------------------------- 1 file changed, 23 insertions(+), 33 deletions(-) (limited to 'dev/alpha_console.cc') diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index fde8af6ae..e05337bfa 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -102,31 +102,24 @@ AlphaConsole::read(Packet &pkt) pkt.time = curTick + pioDelay; Addr daddr = pkt.addr - pioAddr; - uint32_t *data32; - uint64_t *data64; + pkt.allocate(); switch (pkt.size) { case sizeof(uint32_t): - if (!pkt.data) { - data32 = new uint32_t; - pkt.data = (uint8_t*)data32; - } else - data32 = (uint32_t*)pkt.data; - switch (daddr) { case offsetof(AlphaAccess, last_offset): - *data32 = alphaAccess->last_offset; + pkt.set(alphaAccess->last_offset); break; case offsetof(AlphaAccess, version): - *data32 = alphaAccess->version; + pkt.set(alphaAccess->version); break; case offsetof(AlphaAccess, numCPUs): - *data32 = alphaAccess->numCPUs; + pkt.set(alphaAccess->numCPUs); break; case offsetof(AlphaAccess, intrClockFrequency): - *data32 = alphaAccess->intrClockFrequency; + pkt.set(alphaAccess->intrClockFrequency); break; default: /* Old console code read in everyting as a 32bit int @@ -134,62 +127,59 @@ AlphaConsole::read(Packet &pkt) */ pkt.result = BadAddress; } - DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *data32); + DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, + pkt.get()); break; case sizeof(uint64_t): - if (!pkt.data) { - data64 = new uint64_t; - pkt.data = (uint8_t*)data64; - } else - data64 = (uint64_t*)pkt.data; switch (daddr) { case offsetof(AlphaAccess, inputChar): - *data64 = console->console_in(); + pkt.set(console->console_in()); break; case offsetof(AlphaAccess, cpuClock): - *data64 = alphaAccess->cpuClock; + pkt.set(alphaAccess->cpuClock); break; case offsetof(AlphaAccess, mem_size): - *data64 = alphaAccess->mem_size; + pkt.set(alphaAccess->mem_size); break; case offsetof(AlphaAccess, kernStart): - *data64 = alphaAccess->kernStart; + pkt.set(alphaAccess->kernStart); break; case offsetof(AlphaAccess, kernEnd): - *data64 = alphaAccess->kernEnd; + pkt.set(alphaAccess->kernEnd); break; case offsetof(AlphaAccess, entryPoint): - *data64 = alphaAccess->entryPoint; + pkt.set(alphaAccess->entryPoint); break; case offsetof(AlphaAccess, diskUnit): - *data64 = alphaAccess->diskUnit; + pkt.set(alphaAccess->diskUnit); break; case offsetof(AlphaAccess, diskCount): - *data64 = alphaAccess->diskCount; + pkt.set(alphaAccess->diskCount); break; case offsetof(AlphaAccess, diskPAddr): - *data64 = alphaAccess->diskPAddr; + pkt.set(alphaAccess->diskPAddr); break; case offsetof(AlphaAccess, diskBlock): - *data64 = alphaAccess->diskBlock; + pkt.set(alphaAccess->diskBlock); break; case offsetof(AlphaAccess, diskOperation): - *data64 = alphaAccess->diskOperation; + pkt.set(alphaAccess->diskOperation); break; case offsetof(AlphaAccess, outputChar): - *data64 = alphaAccess->outputChar; + pkt.set(alphaAccess->outputChar); break; default: int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / sizeof(alphaAccess->cpuStack[0]); if (cpunum >= 0 && cpunum < 64) - *data64 = alphaAccess->cpuStack[cpunum]; + pkt.set(alphaAccess->cpuStack[cpunum]); else panic("Unknown 64bit access, %#x\n", daddr); } - DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *data64); + DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, + pkt.get()); break; default: pkt.result = BadAddress; @@ -207,7 +197,7 @@ AlphaConsole::write(Packet &pkt) assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); Addr daddr = pkt.addr - pioAddr; - uint64_t val = *(uint64_t *)pkt.data; + uint64_t val = pkt.get(); assert(pkt.size == sizeof(uint64_t)); switch (daddr) { -- cgit v1.2.3