From 602a489573c96d574798c622a70b1b466330fdaf Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Fri, 29 Apr 2005 21:01:43 -0400
Subject: Add suport for no allocation of cache block on a dma read passing
 through a cache from the cpu-side interface

--HG--
extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a
---
 dev/ide_ctrl.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'dev/ide_ctrl.cc')

diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 857cdeb78..ae044427e 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -97,7 +97,8 @@ IdeController::IdeController(Params *p)
 
         dmaInterface = new DMAInterface<Bus>(name() + ".dma",
                                              params()->host_bus,
-                                             params()->host_bus, 1);
+                                             params()->host_bus, 1,
+                                             true);
         pioLatency = params()->pio_latency * params()->host_bus->clockRatio;
     }
 
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