From 602a489573c96d574798c622a70b1b466330fdaf Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Fri, 29 Apr 2005 21:01:43 -0400 Subject: Add suport for no allocation of cache block on a dma read passing through a cache from the cpu-side interface --HG-- extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a --- dev/ns_gige.cc | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'dev/ns_gige.cc') diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 7560b1994..0b416750f 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -120,11 +120,13 @@ NSGigE::NSGigE(Params *p) if (p->payload_bus) dmaInterface = new DMAInterface(name() + ".dma", p->header_bus, - p->payload_bus, 1); + p->payload_bus, 1, + p->dma_no_allocate); else dmaInterface = new DMAInterface(name() + ".dma", p->header_bus, - p->header_bus, 1); + p->header_bus, 1, + p->dma_no_allocate); } else if (p->payload_bus) { pioInterface = newPioInterface(name(), p->hier, p->payload_bus, this, @@ -134,7 +136,8 @@ NSGigE::NSGigE(Params *p) dmaInterface = new DMAInterface(name() + ".dma", p->payload_bus, - p->payload_bus, 1); + p->payload_bus, 1, + p->dma_no_allocate); } @@ -2713,6 +2716,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) Param tx_fifo_size; Param rx_fifo_size; Param m5reg; + Param dma_no_allocate; END_DECLARE_SIM_OBJECT_PARAMS(NSGigE) @@ -2746,7 +2750,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(pci_func, "PCI function code"), INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 131072), INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072), - INIT_PARAM(m5reg, "m5 register") + INIT_PARAM(m5reg, "m5 register"), + INIT_PARAM_DFLT(dma_no_allocate, "Should DMA reads allocate cache lines", true) END_INIT_SIM_OBJECT_PARAMS(NSGigE) @@ -2784,6 +2789,7 @@ CREATE_SIM_OBJECT(NSGigE) params->tx_fifo_size = tx_fifo_size; params->rx_fifo_size = rx_fifo_size; params->m5reg = m5reg; + params->dma_no_allocate = dma_no_allocate; return new NSGigE(params); } -- cgit v1.2.3