From f806a25c9edb3a9a9f5bc34b88340be6b24a2022 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <binkertn@umich.edu>
Date: Mon, 21 Nov 2005 23:43:15 -0500
Subject: add support for delaying pio writes until the cache access occurs

dev/ns_gige.cc:
    add support for delaying pio writes until the cache access occurs
    the only write we delay are for CR_TXE and CR_RXE
dev/sinic.cc:
dev/sinic.hh:
    the txPioRequest and rxPioRequest things were more or less bogus
    add support for delaying pio writes until the cache access occurs
dev/sinicreg.hh:
    Add delay_read and delay_write to the register information struct
    for now, we won't delay any reads, and we'll delay the writes that
    initiate DMAs
python/m5/objects/Ethernet.py:
    add a parameter to delay pio writes until the timing access
    actually occurs.

--HG--
extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d
---
 dev/ns_gige.cc | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 53 insertions(+), 8 deletions(-)

(limited to 'dev/ns_gige.cc')

diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index c8ff04ec5..979bb6b7a 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -130,6 +130,7 @@ NSGigE::NSGigE(Params *p)
     } else if (p->payload_bus)
         panic("Must define a header bus if defining a payload bus");
 
+    pioDelayWrite = p->pio_delay_write && pioInterface;
 
     intrDelay = p->intr_delay;
     dmaReadDelay = p->dma_read_delay;
@@ -801,6 +802,13 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
     } else if (daddr > 0x3FC)
         panic("Something is messed up!\n");
 
+    if (pioDelayWrite) {
+        int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
+        if (cpu >= writeQueue.size())
+            writeQueue.resize(cpu + 1);
+        writeQueue[cpu].push_back(RegWriteData(daddr, *(uint32_t *)data));
+    }
+
     if (req->size == sizeof(uint32_t)) {
         uint32_t reg = *(uint32_t *)data;
         uint16_t rfaddr;
@@ -813,20 +821,24 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
             if (reg & CR_TXD) {
                 txEnable = false;
             } else if (reg & CR_TXE) {
-                txEnable = true;
+                if (!pioDelayWrite) {
+                    txEnable = true;
 
-                // the kernel is enabling the transmit machine
-                if (txState == txIdle)
-                    txKick();
+                    // the kernel is enabling the transmit machine
+                    if (txState == txIdle)
+                        txKick();
+                }
             }
 
             if (reg & CR_RXD) {
                 rxEnable = false;
             } else if (reg & CR_RXE) {
-                rxEnable = true;
+                if (!pioDelayWrite) {
+                    rxEnable = true;
 
-                if (rxState == rxIdle)
-                    rxKick();
+                    if (rxState == rxIdle)
+                        rxKick();
+                }
             }
 
             if (reg & CR_TXR)
@@ -2934,8 +2946,38 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
 Tick
 NSGigE::cacheAccess(MemReqPtr &req)
 {
+    Addr daddr = req->paddr & 0xfff;
     DPRINTF(EthernetPIO, "timing access to paddr=%#x (daddr=%#x)\n",
-            req->paddr, req->paddr - addr);
+            req->paddr, daddr);
+
+    if (!pioDelayWrite || !req->cmd.isWrite())
+        return curTick + pioLatency;
+
+    int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
+    std::list<RegWriteData> &wq = writeQueue[cpu];
+    if (wq.empty())
+        panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr);
+
+    const RegWriteData &data = wq.front();
+    if (data.daddr != daddr)
+        panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x",
+              cpu, data.daddr, daddr);
+
+    if (daddr == CR) {
+        if ((data.value & (CR_TXD | CR_TXE)) == CR_TXE) {
+            txEnable = true;
+            if (txState == txIdle)
+                txKick();
+        }
+
+        if ((data.value & (CR_RXD | CR_RXE)) == CR_RXE) {
+            rxEnable = true;
+            if (rxState == rxIdle)
+                rxKick();
+        }
+    }
+
+    wq.pop_front();
     return curTick + pioLatency;
 }
 
@@ -2995,6 +3037,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
     Param<Tick> dma_write_factor;
     Param<bool> dma_no_allocate;
     Param<Tick> pio_latency;
+    Param<bool> pio_delay_write;
     Param<Tick> intr_delay;
 
     Param<Tick> rx_delay;
@@ -3034,6 +3077,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
     INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
     INIT_PARAM(dma_no_allocate, "Should DMA reads allocate cache lines"),
     INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
+    INIT_PARAM(pio_delay_write, ""),
     INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
 
     INIT_PARAM(rx_delay, "Receive Delay"),
@@ -3077,6 +3121,7 @@ CREATE_SIM_OBJECT(NSGigE)
     params->dma_write_factor = dma_write_factor;
     params->dma_no_allocate = dma_no_allocate;
     params->pio_latency = pio_latency;
+    params->pio_delay_write = pio_delay_write;
     params->intr_delay = intr_delay;
 
     params->rx_delay = rx_delay;
-- 
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