From 6a8ae7a6a040876e697dfa8b837e1ba1bd7e1fd5 Mon Sep 17 00:00:00 2001 From: Miguel Serrano Date: Thu, 28 Jul 2005 11:47:06 -0400 Subject: ghgfsdf dev/pciconfigall.cc: removed union. dev/pcidev.cc: . dev/rtcreg.h: more macros to avoid magic numbers. dev/tsunami_io.cc: replaced magic numbers, no more advancing RTC as it isn't reaaly necessary. dev/tsunami_io.hh: removed declarations of things that go unused. dev/uart8250.cc: reading the Interrupt ID register should clear TX interrupt flag. dev/uart8250.hh: useful #defines. kern/freebsd/freebsd_system.cc: kern/freebsd/freebsd_system.hh: nothing. python/m5/objects/Pci.py: new PciFake. --HG-- extra : convert_revision : 88259704f5b215591d1416360180810fcda14d26 --- dev/rtcreg.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'dev/rtcreg.h') diff --git a/dev/rtcreg.h b/dev/rtcreg.h index 0b33c25b2..032e22ab5 100644 --- a/dev/rtcreg.h +++ b/dev/rtcreg.h @@ -36,8 +36,22 @@ #define RTC_DOM 0x07 #define RTC_MON 0x08 #define RTC_YEAR 0x09 + #define RTC_CNTRL_REGA 0x0A +#define RTCA_1024HZ 0x06 /* 1024Hz periodic interrupt frequency */ +#define RTCA_32768HZ 0x20 /* 22-stage divider, 32.768KHz timebase */ +#define RTCA_UIP 0x80 /* 1 = date and time update in progress */ + #define RTC_CNTRL_REGB 0x0B +#define RTCB_DST 0x01 /* USA Daylight Savings Time enable */ +#define RTCB_24HR 0x02 /* 0 = 12 hours, 1 = 24 hours */ +#define RTCB_BIN 0x04 /* 0 = BCD, 1 = Binary coded time */ +#define RTCB_SQWE 0x08 /* 1 = output sqare wave at SQW pin */ +#define RTCB_UPDT_IE 0x10 /* 1 = enable update-ended interrupt */ +#define RTCB_ALRM_IE 0x20 /* 1 = enable alarm interrupt */ +#define RTCB_PRDC_IE 0x40 /* 1 = enable periodic clock interrupt */ +#define RTCB_NO_UPDT 0x80 /* stop clock updates */ + #define RTC_CNTRL_REGC 0x0C #define RTC_CNTRL_REGD 0x0D -- cgit v1.2.3