From 3a0102536bdbf00629e6ba944bd55ee0ec77fb52 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <binkertn@umich.edu>
Date: Mon, 20 Feb 2006 23:41:50 -0500
Subject: Get rid of the code that delays PIO write accesses until the cache
 access occurs.  The fundamental problem is that a subsequent read that occurs
 functionally will get a functionally incorrect result that can break driver
 code.

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
    get rid of pio_delay write and the associated code to move
    the write to the cache access function
dev/sinicreg.hh:
    no more write delays
python/m5/objects/Ethernet.py:
    get rid of pio_delay write

--HG--
extra : convert_revision : 1dcb51b8f4514e717bc334a782dfdf06d29ae69d
---
 dev/sinic.hh | 12 ------------
 1 file changed, 12 deletions(-)

(limited to 'dev/sinic.hh')

diff --git a/dev/sinic.hh b/dev/sinic.hh
index 7935a7cdc..06751a955 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -283,17 +283,6 @@ class Device : public Base
     void regWrite(Addr daddr, int cpu, const uint8_t *data);
     Tick cacheAccess(MemReqPtr &req);
 
-  protected:
-    struct RegWriteData {
-        Addr daddr;
-        uint64_t value;
-        RegWriteData(Addr da, uint64_t val) : daddr(da), value(val) {}
-    };
-
-    std::vector<std::list<RegWriteData> > writeQueue;
-
-    bool pioDelayWrite;
-
 /**
  * Statistics
  */
@@ -349,7 +338,6 @@ class Device : public Base
         Bus *header_bus;
         Bus *payload_bus;
         Tick pio_latency;
-        bool pio_delay_write;
         PhysicalMemory *physmem;
         IntrControl *intctrl;
         bool rx_filter;
-- 
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