From 3ccc0b1f968e3efaeccda65e06f862c899678312 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Tue, 27 Jan 2004 21:36:46 -0500
Subject: Add support for RTC to interrupt, HACK in alpha_console temporary

dev/alpha_console.cc:
    Fix reference to tlaserclock, HACK FOR NOW
dev/alpha_console.hh:
    fix reference to tlaser_clock, HACK FOR NOW
dev/tsunami.cc:
    Add proper tsunami chip pointers
dev/tsunami.hh:
    add proper tsunami chip pointers add RTC interrupt capabilities
dev/tsunami_cchip.cc:
    Add proper Interrupt for RTC
dev/tsunami_cchip.hh:
    Add proper interrupt for RTC
dev/tsunami_io.cc:
dev/tsunami_io.hh:
    Make RTC interrupt
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
    Add back pointer to tsunami

--HG--
extra : convert_revision : 2b0a8616b0bed8d9962ee5ca643dce56b9922d52
---
 dev/tsunami_cchip.cc | 25 ++++++++++++++++++-------
 1 file changed, 18 insertions(+), 7 deletions(-)

(limited to 'dev/tsunami_cchip.cc')

diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index ca9eae184..6559f3809 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -17,15 +17,16 @@
 #include "dev/tsunami_cchip.hh"
 #include "dev/tsunamireg.h"
 #include "dev/tsunami.hh"
+#include "cpu/intr_control.hh"
 #include "mem/functional_mem/memory_control.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
 
-TsunamiCChip::TsunamiCChip(const string &name, /*Tsunami *t,*/
+TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t,
                        Addr addr, Addr mask, MemoryController *mmu)
-    : MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */
+    : MmapDevice(name, addr, mask, mmu), tsunami(t)
 {
     for(int i=0; i < Tsunami::Max_CPUs; i++) {
         dim[i] = 0;
@@ -33,6 +34,11 @@ TsunamiCChip::TsunamiCChip(const string &name, /*Tsunami *t,*/
     }
 
     drir = 0;
+    misc = 0;
+    RTCInterrupting = false;
+
+    //Put back pointer in tsunami
+    tsunami->cchip = this;
 }
 
 Fault
@@ -56,7 +62,7 @@ TsunamiCChip::read(MemReqPtr req, uint8_t *data)
                   panic("TSDEV_CC_MTR not implemeted\n");
                    return No_Fault;
               case TSDEV_CC_MISC:
-                  panic("TSDEV_CC_MISC not implemented\n");
+                *(uint64_t*)data = misc;
                   return No_Fault;
               case TSDEV_CC_AAR0:
               case TSDEV_CC_AAR1:
@@ -141,7 +147,12 @@ TsunamiCChip::write(MemReqPtr req, const uint8_t *data)
                   panic("TSDEV_CC_MTR write not implemented\n");
                    return No_Fault;
               case TSDEV_CC_MISC:
-                  panic("TSDEV_CC_MISC write not implemented\n");
+                //If it is the seventh bit, clear the RTC interrupt
+                if ((*(uint64_t*) data) & (1<<7)) {
+                    RTCInterrupting = false;
+                    tsunami->intrctrl->clear(0, TheISA::INTLEVEL_IRQ2, 0);
+                    misc &= ~(1<<7);
+                } else panic("TSDEV_CC_MISC write not implemented\n");
                   return No_Fault;
               case TSDEV_CC_AAR0:
               case TSDEV_CC_AAR1:
@@ -216,7 +227,7 @@ TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 
- //   SimObjectParam<Tsunami *> tsunami;
+    SimObjectParam<Tsunami *> tsunami;
     SimObjectParam<MemoryController *> mmu;
     Param<Addr> addr;
     Param<Addr> mask;
@@ -225,7 +236,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 
-//    INIT_PARAM(tsunami, "Tsunami"),
+    INIT_PARAM(tsunami, "Tsunami"),
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(addr, "Device Address"),
     INIT_PARAM(mask, "Address Mask")
@@ -234,7 +245,7 @@ END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 
 CREATE_SIM_OBJECT(TsunamiCChip)
 {
-    return new TsunamiCChip(getInstanceName(), /*tsunami,*/ addr, mask, mmu);
+    return new TsunamiCChip(getInstanceName(), tsunami, addr, mask, mmu);
 }
 
 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
-- 
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