From 13f8dc981fc898e6e200689d305b39f0718f8c83 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <binkertn@umich.edu>
Date: Mon, 12 Jul 2004 22:58:22 -0400
Subject: make the cache access latency a parameter that is based on bus ticks
 for the most commonly accessed devices.

dev/baddev.cc:
    Get rid of the constant cache access latency.
    For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
    make the cache access latency a parameter that is based on bus
    ticks.
dev/io_device.cc:
dev/io_device.hh:
    add an io latency variable
dev/ns_gige.hh:
    this moved to io_device.hh

--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
---
 dev/tsunami_io.cc | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'dev/tsunami_io.cc')

diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 4c798a852..105e3b5b7 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -160,7 +160,8 @@ TsunamiIO::ClockEvent::unserialize(Checkpoint *cp, const std::string &section)
 }
 
 TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
-                     Addr a, MemoryController *mmu, HierParams *hier, Bus *bus)
+                     Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
+                     Tick pio_latency)
     : PioDevice(name), addr(a), tsunami(t), rtc(t)
 {
     mmu->add_child(this, Range<Addr>(addr, addr + size));
@@ -169,6 +170,7 @@ TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
         pioInterface = newPioInterface(name, hier, bus, this,
                                        &TsunamiIO::cacheAccess);
         pioInterface->addAddrRange(addr, addr + size - 1);
+        pioLatency = pio_latency * bus->clockRatio;
     }
 
     // set the back pointer from tsunami to myself
@@ -425,7 +427,7 @@ TsunamiIO::clearPIC(uint8_t bitvector)
 Tick
 TsunamiIO::cacheAccess(MemReqPtr &req)
 {
-    return curTick + 1000;
+    return curTick + pioLatency;
 }
 
 void
@@ -476,6 +478,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
     SimObjectParam<MemoryController *> mmu;
     Param<Addr> addr;
     SimObjectParam<Bus*> io_bus;
+    Param<Tick> pio_latency;
     SimObjectParam<HierParams *> hier;
 
 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
@@ -488,6 +491,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(addr, "Device Address"),
     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
@@ -495,7 +499,7 @@ END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
 CREATE_SIM_OBJECT(TsunamiIO)
 {
     return new TsunamiIO(getInstanceName(), tsunami, time,  addr, mmu, hier,
-                         io_bus);
+                         io_bus, pio_latency);
 }
 
 REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
-- 
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