From db940dd0b08f020326c20bc983af5d3483656491 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Fri, 20 Feb 2004 14:28:59 -0500 Subject: Add support for IPI's and extend RTC to interrupt all Processors dev/tsunami_cchip.cc: Add support for IPI, making changes to read/write to MISC register Particularly the IPREQ, IPINTR, and ITINTR subfields dev/tsunami_cchip.hh: Make an array to keep track of the number of outstanding IPI's, Extend RTC to interrupt all processors, not just cpu0 dev/tsunami_io.cc: Extend RTC to interrupt all present proccessors, not just cpu0 --HG-- extra : convert_revision : 0715cbf0abb06002c0fb0b05ef369304cdf75001 --- dev/tsunami_io.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'dev/tsunami_io.cc') diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index fa87a72c4..41acf1fae 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -65,10 +65,14 @@ TsunamiIO::RTCEvent::process() DPRINTF(MC146818, "RTC Timer Interrupt\n"); schedule(curTick + ticksPerSecond/RTC_RATE); //Actually interrupt the processor here - if (!tsunami->cchip->RTCInterrupting) { - tsunami->cchip->misc |= 1 << 7; - tsunami->cchip->RTCInterrupting = true; - tsunami->intrctrl->post(0, TheISA::INTLEVEL_IRQ2, 0); + int size = tsunami->intrctrl->cpu->system->execContexts.size(); + + for (int i = 0; i < size; i++) { + if (!tsunami->cchip->RTCInterrupting[i]) { + tsunami->cchip->misc |= 16 << i; + tsunami->cchip->RTCInterrupting[i] = true; + tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); + } } } -- cgit v1.2.3