From 1ded394fc398f5bbbecef84709824ac7d028dd1e Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Mon, 9 Feb 2004 13:40:58 -0500
Subject: Some changes to for linux 2.6.2

dev/pcidev.cc:
    Linux 2.6 writes the latency timer, so it was added to the list of
    allowable writes
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
    A couple of changes so that the new linux autoconf serial driver thinks
    that the serial port exists and configures it

--HG--
extra : convert_revision : 6c026ef754e31de56c9b837ceb8f6be48c8d8d9c
---
 dev/tsunami_uart.cc | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

(limited to 'dev/tsunami_uart.cc')

diff --git a/dev/tsunami_uart.cc b/dev/tsunami_uart.cc
index 30fbb70d6..0a0b5ffef 100644
--- a/dev/tsunami_uart.cc
+++ b/dev/tsunami_uart.cc
@@ -36,6 +36,7 @@ TsunamiUart::TsunamiUart(const string &name, SimConsole *c,
     : MmapDevice(name, addr, mask, mmu),
       cons(c), status_store(0), valid_char(false)
 {
+    IER = 0;
 }
 
 Fault
@@ -95,8 +96,8 @@ TsunamiUart::read(MemReqPtr &req, uint8_t *data)
         }
 
       case 0x8: // Data register (RX)
-        if (!valid_char)
-            panic("Invalid character");
+//	if (!valid_char)
+//	    panic("Invalid character");
 
         DPRINTF(TsunamiUart, "read data register \'%c\' %#02x\n",
                 isprint(next_char) ? next_char : ' ', next_char);
@@ -106,7 +107,18 @@ TsunamiUart::read(MemReqPtr &req, uint8_t *data)
         return No_Fault;
 
       case 0x9: // Interrupt Enable Register
-        *data = 0;
+        // This is the lovely way linux checks there is actually a serial
+        // port at the desired address
+        if (IER == 0)
+            *data = 0;
+        else if (IER == 0x0F)
+            *data = 0x0F;
+        else
+            *data = 0;
+        return No_Fault;
+      case 0xA:
+        //*data = 2<<6; // This means a 8250 serial port, do we want a 16550?
+        *data = 0; // This means a 8250 serial port, do we want a 16550?
         return No_Fault;
     }
     *data = 0;
@@ -145,7 +157,7 @@ TsunamiUart::write(MemReqPtr &req, const uint8_t *data)
 
           default:
             DPRINTF(TsunamiUart, "writing status register %#x \n",
-                    *(uint64_t *)data);
+                    *(uint8_t *)data);
             return No_Fault;
         }
 
@@ -154,6 +166,7 @@ TsunamiUart::write(MemReqPtr &req, const uint8_t *data)
         return No_Fault;
       case 0x9: // DLM
         DPRINTF(TsunamiUart, "writing to DLM/IER %#x\n", *(uint8_t*)data);
+        IER = *(uint8_t*)data;
         return No_Fault;
       case 0xc: // MCR
         DPRINTF(TsunamiUart, "writing to MCR %#x\n", *(uint8_t*)data);
-- 
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