From 3c7071a6be21fc0c87753758fc09ff28890edc99 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sun, 9 May 2004 20:14:18 -0400 Subject: Added ULL for 64bit ints Added function to skip determine_cpu_caches(). We may have to update this in the future: see note below. arch/alpha/alpha_memory.cc: dev/ide_ctrl.cc: dev/tsunamireg.h: Added ULL for 64bit ints kern/linux/linux_system.cc: Added a function to skip determine_cpu_caches, right now it is only used for printing in proc, however in the future we may either want to implement the SC_CTL IPR register or manually set alpha_l1i_cacheshape, alpha_l1d_cacheshape, alpha_l2_cacheshape, alpha_l3_cacheshape to ((size << 10) | (linesize>>1)<<4 | way) kern/linux/linux_system.hh: added event to skip determine_cpu_caches() --HG-- extra : convert_revision : 1065f2091bbe6832b730af490f5b4672c2afedce --- dev/tsunamireg.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'dev/tsunamireg.h') diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h index c74279ecf..1207ebf9f 100644 --- a/dev/tsunamireg.h +++ b/dev/tsunamireg.h @@ -2,7 +2,7 @@ #ifndef __TSUNAMIREG_H__ #define __TSUNAMIREG_H__ -#define ALPHA_K0SEG_BASE 0xfffffc0000000000 +#define ALPHA_K0SEG_BASE 0xfffffc0000000000ULL // CChip Registers #define TSDEV_CC_CSR 0x00 @@ -101,8 +101,8 @@ #define RTC_CONTROL_REGISTERD 13 // control register D #define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1 -#define PCHIP_PCI0_MEMORY 0x10000000000 -#define PCHIP_PCI0_IO 0x101FC000000 +#define PCHIP_PCI0_MEMORY 0x10000000000ULL +#define PCHIP_PCI0_IO 0x101FC000000ULL #define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY #define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO -- cgit v1.2.3