From 32b52fe7126091692c0a76314bb3692fa3f70d27 Mon Sep 17 00:00:00 2001 From: Benjamin Nash Date: Wed, 13 Jul 2005 12:30:13 -0400 Subject: Various changes to m5/dev files to work with FreeBSD. dev/ide_ctrl.cc: dev/ide_disk.cc: dev/pcidev.cc: Made endian-independent. dev/ide_disk.hh: fixed. dev/pciconfigall.cc: The data to write is contained in a 32-bit unsigned int now. The union method would not have worked on big-endian machines. dev/pcidev.hh: Fixed typo. dev/tsunami_io.cc: Return zero on RTC alarm reads. dev/uart8250.cc: Fix uart interrupt handling. --HG-- extra : convert_revision : b5c08e8e77644c399c20888666406805ff1b6649 --- dev/uart8250.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'dev/uart8250.cc') diff --git a/dev/uart8250.cc b/dev/uart8250.cc index 99e3bd017..63756042a 100644 --- a/dev/uart8250.cc +++ b/dev/uart8250.cc @@ -88,7 +88,7 @@ Uart8250::IntrEvent::process() void Uart8250::IntrEvent::scheduleIntr() { - static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450); + static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 600); DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit, curTick + interval); if (!scheduled()) @@ -146,10 +146,11 @@ Uart8250::read(MemReqPtr &req, uint8_t *data) break; case 0x2: // Intr Identification Register (IIR) DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status); - if (status) - *(uint8_t*)data = 0; + status &= ~TX_INT; + if (status & RX_INT) + *(uint8_t*)data = 0x4; else - *(uint8_t*)data = 1; + *(uint8_t*)data = 0x1; break; case 0x3: // Line Control Register (LCR) *(uint8_t*)data = LCR; -- cgit v1.2.3