From 3ef950abba818e0f6b0fa4c8acc39cfb6ae11a28 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Sat, 16 Oct 2004 19:10:51 -0500
Subject: Fixes for bigendian platforms

arch/alpha/vtophys.cc:
    PGOFSET -> ALPHA_PGOFSET to avoid include file problems
base/callback.hh:
    Added  a class to create a callback from a function
base/intmath.hh:
    make FloorLog2 inlined
dev/pcidev.cc:
    more work in getting pciconfig space happy with different endiannesses
dev/uart.cc:
    used an incorrect size for write uint64_t instead of uint8_t
sim/system.cc:
    when writing things into system data structures we need to pay
    attention to endianness

--HG--
extra : convert_revision : 52f441b5789c45db30ef2f6fd4975cbc7323a381
---
 dev/pcidev.cc | 28 ++++++++++++++--------------
 dev/uart.cc   |  2 +-
 2 files changed, 15 insertions(+), 15 deletions(-)

(limited to 'dev')

diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index 7b13aac80..950d98b54 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -129,7 +129,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
           case PCI0_INTERRUPT_LINE:
           case PCI_CACHE_LINE_SIZE:
           case PCI_LATENCY_TIMER:
-            *(uint8_t *)&config.data[offset] = byte_value;
+            *(uint8_t *)&config.data[offset] = htoa(byte_value);
             break;
 
           default:
@@ -142,7 +142,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
           case PCI_COMMAND:
           case PCI_STATUS:
           case PCI_CACHE_LINE_SIZE:
-            *(uint16_t *)&config.data[offset] = half_value;
+            *(uint16_t *)&config.data[offset] = htoa(half_value);
             break;
 
           default:
@@ -166,21 +166,21 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
             // to size of memory it needs
             if (word_value == 0xffffffff) {
                 // This is I/O Space, bottom two bits are read only
-                if (config.data[offset] & 0x1) {
-                    *(uint32_t *)&config.data[offset] =
+                if (htoa(config.data[offset]) & 0x1) {
+                    *(uint32_t *)&config.data[offset] = htoa(
                         ~(BARSize[barnum] - 1) |
-                        (config.data[offset] & 0x3);
+                        (htoa(config.data[offset]) & 0x3));
                 } else {
                     // This is memory space, bottom four bits are read only
-                    *(uint32_t *)&config.data[offset] =
+                    *(uint32_t *)&config.data[offset] = htoa(
                         ~(BARSize[barnum] - 1) |
-                        (config.data[offset] & 0xF);
+                        (htoa(config.data[offset]) & 0xF));
                 }
             } else {
                 // This is I/O Space, bottom two bits are read only
-                if(config.data[offset] & 0x1) {
-                    *(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
-                        (config.data[offset] & 0x3);
+                if(htoa(config.data[offset]) & 0x1) {
+                    *(uint32_t *)&config.data[offset] = htoa((word_value & ~0x3) |
+                        (htoa(config.data[offset]) & 0x3));
 
                     if (word_value & ~0x1) {
                         Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
@@ -205,8 +205,8 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
 
                 } else {
                     // This is memory space, bottom four bits are read only
-                    *(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
-                        (config.data[offset] & 0xF);
+                    *(uint32_t *)&config.data[offset] = htoa((word_value & ~0xF) |
+                        (htoa(config.data[offset]) & 0xF));
 
                     if (word_value & ~0x3) {
                         Addr base_addr = (word_value & ~0x3) +
@@ -238,14 +238,14 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
             if (word_value == 0xfffffffe)
                 *(uint32_t *)&config.data[offset] = 0xffffffff;
             else
-                *(uint32_t *)&config.data[offset] = word_value;
+                *(uint32_t *)&config.data[offset] = htoa(word_value);
             break;
 
           case PCI_COMMAND:
             // This could also clear some of the error bits in the Status
             // register. However they should never get set, so lets ignore
             // it for now
-            *(uint16_t *)&config.data[offset] = half_value;
+            *(uint16_t *)&config.data[offset] = htoa(half_value);
             break;
 
           default:
diff --git a/dev/uart.cc b/dev/uart.cc
index fca856d5d..f03e3899f 100644
--- a/dev/uart.cc
+++ b/dev/uart.cc
@@ -287,7 +287,7 @@ Uart::write(MemReqPtr &req, const uint8_t *data)
     switch (daddr) {
         case 0x0:
             if (!(LCR & 0x80)) { // write byte
-                cons->out(*(uint64_t *)data);
+                cons->out(*(uint8_t *)data);
                 platform->clearConsoleInt();
                 status &= ~TX_INT;
                 if (UART_IER_THRI & IER)
-- 
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