From 40174f119de13d9d295a2e68c6410b9e4aa9ff82 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 11 Aug 2004 10:14:26 -0400 Subject: cleanup interrupt code for gigabit device dev/ns_gige.cc: Clean up the interrupt code. Do a better job determining when coalescing should happen. Remove some bogus comments Stop using magic numbers in initialization and comment what the various numbers do dev/ns_gige_reg.h: #define describing which interrupts cannot be delayed and which interrrupts we don't implement --HG-- extra : convert_revision : eb196afa0bf448e1849dd2bd30dde32134effee7 --- dev/ns_gige.cc | 143 +++++++++--------------------------------------------- dev/ns_gige_reg.h | 13 +++-- 2 files changed, 29 insertions(+), 127 deletions(-) (limited to 'dev') diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 22c0ba35d..f7f56d39b 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -925,74 +925,25 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data) void NSGigE::devIntrPost(uint32_t interrupts) { - bool delay = false; - if (interrupts & ISR_RESERVE) panic("Cannot set a reserved interrupt"); - if (interrupts & ISR_TXRCMP) - regs.isr |= ISR_TXRCMP; - - if (interrupts & ISR_RXRCMP) - regs.isr |= ISR_RXRCMP; - -//ISR_DPERR not implemented -//ISR_SSERR not implemented -//ISR_RMABT not implemented -//ISR_RXSOVR not implemented -//ISR_HIBINT not implemented -//ISR_PHY not implemented -//ISR_PME not implemented - - if (interrupts & ISR_SWI) - regs.isr |= ISR_SWI; - -//ISR_MIB not implemented -//ISR_TXURN not implemented - - if (interrupts & ISR_TXIDLE) - regs.isr |= ISR_TXIDLE; - - if (interrupts & ISR_TXERR) - regs.isr |= ISR_TXERR; - - if (interrupts & ISR_TXDESC) - regs.isr |= ISR_TXDESC; - - if (interrupts & ISR_TXOK) { - regs.isr |= ISR_TXOK; - delay = true; - } + if (interrupts & ISR_NOIMPL) + warn("interrupt not implemented %#x\n", interrupts); - if (interrupts & ISR_RXORN) - regs.isr |= ISR_RXORN; + interrupts &= ~ISR_NOIMPL; + regs.isr |= interrupts; - if (interrupts & ISR_RXIDLE) - regs.isr |= ISR_RXIDLE; - -//ISR_RXEARLY not implemented - - if (interrupts & ISR_RXERR) - regs.isr |= ISR_RXERR; - - if (interrupts & ISR_RXDESC) - regs.isr |= ISR_RXDESC; - - if (interrupts & ISR_RXOK) { - delay = true; - regs.isr |= ISR_RXOK; - } + DPRINTF(EthernetIntr, + "interrupt written to ISR: intr=%#x isr=%#x imr=%#x\n", + interrupts, regs.isr, regs.imr); if ((regs.isr & regs.imr)) { Tick when = curTick; - if (delay) + if (!(regs.isr & regs.imr & ISR_NODELAY)) when += intrDelay; cpuIntrPost(when); } - - DPRINTF(EthernetIntr, - "interrupt written to ISR: intr=%#x isr=%#x imr=%#x\n", - interrupts, regs.isr, regs.imr); } void @@ -1001,54 +952,8 @@ NSGigE::devIntrClear(uint32_t interrupts) if (interrupts & ISR_RESERVE) panic("Cannot clear a reserved interrupt"); - if (interrupts & ISR_TXRCMP) - regs.isr &= ~ISR_TXRCMP; - - if (interrupts & ISR_RXRCMP) - regs.isr &= ~ISR_RXRCMP; - -//ISR_DPERR not implemented -//ISR_SSERR not implemented -//ISR_RMABT not implemented -//ISR_RXSOVR not implemented -//ISR_HIBINT not implemented -//ISR_PHY not implemented -//ISR_PME not implemented - - if (interrupts & ISR_SWI) - regs.isr &= ~ISR_SWI; - -//ISR_MIB not implemented -//ISR_TXURN not implemented - - if (interrupts & ISR_TXIDLE) - regs.isr &= ~ISR_TXIDLE; - - if (interrupts & ISR_TXERR) - regs.isr &= ~ISR_TXERR; - - if (interrupts & ISR_TXDESC) - regs.isr &= ~ISR_TXDESC; - - if (interrupts & ISR_TXOK) - regs.isr &= ~ISR_TXOK; - - if (interrupts & ISR_RXORN) - regs.isr &= ~ISR_RXORN; - - if (interrupts & ISR_RXIDLE) - regs.isr &= ~ISR_RXIDLE; - -//ISR_RXEARLY not implemented - - if (interrupts & ISR_RXERR) - regs.isr &= ~ISR_RXERR; - - if (interrupts & ISR_RXDESC) - regs.isr &= ~ISR_RXDESC; - - if (interrupts & ISR_RXOK) - regs.isr &= ~ISR_RXOK; + interrupts &= ~ISR_NOIMPL; + regs.isr &= ~interrupts; DPRINTF(EthernetIntr, "interrupt cleared from ISR: intr=%x isr=%x imr=%x\n", @@ -1134,9 +1039,8 @@ NSGigE::cpuInterrupt() // Send interrupt cpuPendingIntr = true; - /** @todo rework the intctrl to be tsunami ok */ - //intctrl->post(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_ETHERNET); - DPRINTF(EthernetIntr, "Posting interrupts to cchip!\n"); + + DPRINTF(EthernetIntr, "posting cchip interrupt\n"); tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine); } @@ -1147,9 +1051,8 @@ NSGigE::cpuIntrClear() return; cpuPendingIntr = false; - /** @todo rework the intctrl to be tsunami ok */ - //intctrl->clear(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_ETHERNET); - DPRINTF(EthernetIntr, "clearing all interrupts from cchip\n"); + + DPRINTF(EthernetIntr, "clearing cchip interrupt\n"); tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine); } @@ -1193,15 +1096,15 @@ void NSGigE::regsReset() { memset(®s, 0, sizeof(regs)); - regs.config = 0x80000000; - regs.mear = 0x12; - regs.isr = 0x00608000; - regs.txcfg = 0x120; - regs.rxcfg = 0x4; - regs.srr = 0x0103; - regs.mibc = 0x2; - regs.vdr = 0x81; - regs.tesr = 0xc000; + regs.config = CFG_LNKSTS; + regs.mear = MEAR_MDDIR | MEAR_EEDO; + regs.txcfg = 0x120; // set drain threshold to 1024 bytes and + // fill threshold to 32 bytes + regs.rxcfg = 0x4; // set drain threshold to 16 bytes + regs.srr = 0x0103; // set the silicon revision to rev B or 0x103 + regs.mibc = MIBC_FRZ; + regs.vdr = 0x81; // set the vlan tag type to 802.1q + regs.tesr = 0xc000; // TBI capable of both full and half duplex extstsEnable = false; acceptBroadcast = false; diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h index c87dfe960..01577fa39 100644 --- a/dev/ns_gige_reg.h +++ b/dev/ns_gige_reg.h @@ -55,17 +55,13 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ - - - - /* @file * Ethernet device register definitions for the National * Semiconductor DP83820 Ethernet controller */ -#ifndef _NS_GIGE_H -#define _NS_GIGE_H_ +#ifndef __DEV_NS_GIGE_REG_H__ +#define __DEV_NS_GIGE_REG_H__ /* * Configuration Register Map @@ -220,6 +216,9 @@ #define ISR_RXDESC 0x00000002 #define ISR_RXOK 0x00000001 #define ISR_ALL 0x7FFFFFFF +#define ISR_NODELAY (ISR_ALL & ~(ISR_RXOK|ISR_RXDESC|ISR_TXOK|ISR_TXDESC)) +#define ISR_NOIMPL (~(ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \ + ISR_RXIDLE|ISR_RXDESC|ISR_RXOK)) /* transmit configuration register */ #define TXCFG_CSI 0x80000000 @@ -369,4 +368,4 @@ struct ns_desc { /* speed status */ #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) -#endif /* _NS_GIGE_H_ */ +#endif /* __DEV_NS_GIGE_REG_H__ */ -- cgit v1.2.3