From 4f43bc65eaf67c2458177f6e77b2ca611cb21ef7 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 18 Oct 2005 21:01:05 -0400 Subject: use the dedicated flag, no more exposing the m5reg directly dev/ns_gige.cc: stop exposing the m5reg to the configuration stuff and build it based on exposed flags. Expose dedicated now. dev/ns_gige.hh: goodbye m5reg hello dedicated dev/ns_gige_reg.h: Flags for the M5REG --HG-- extra : convert_revision : 11134fe67cdf5291caacf9b3041739c437b983e3 --- dev/ns_gige.cc | 10 ++++++---- dev/ns_gige.hh | 2 +- dev/ns_gige_reg.h | 4 ++++ 3 files changed, 11 insertions(+), 5 deletions(-) (limited to 'dev') diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index d67c6cf95..dfc4af5fb 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -771,7 +771,9 @@ NSGigE::read(MemReqPtr &req, uint8_t *data) break; case M5REG: - reg = params()->m5reg; + reg = 0; + if (params()->dedicated) + reg |= M5REG_DEDICATED; break; default: @@ -3009,7 +3011,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) Param pci_func; Param tx_fifo_size; Param rx_fifo_size; - Param m5reg; + Param dedicated; Param dma_no_allocate; END_DECLARE_SIM_OBJECT_PARAMS(NSGigE) @@ -3043,7 +3045,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(pci_func, "PCI function code"), INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 131072), INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072), - INIT_PARAM(m5reg, "m5 register"), + INIT_PARAM(dedicated, "dedicate a kernel thread to the driver"), INIT_PARAM_DFLT(dma_no_allocate, "Should DMA reads allocate cache lines", true) END_INIT_SIM_OBJECT_PARAMS(NSGigE) @@ -3081,7 +3083,7 @@ CREATE_SIM_OBJECT(NSGigE) params->eaddr = hardware_address; params->tx_fifo_size = tx_fifo_size; params->rx_fifo_size = rx_fifo_size; - params->m5reg = m5reg; + params->dedicated = dedicated; params->dma_no_allocate = dma_no_allocate; return new NSGigE(params); } diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index 111003432..a04b52fe9 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -385,7 +385,7 @@ class NSGigE : public PciDev Net::EthAddr eaddr; uint32_t tx_fifo_size; uint32_t rx_fifo_size; - uint32_t m5reg; + bool dedicated; bool dma_no_allocate; }; diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h index 54ffb9075..f919ff086 100644 --- a/dev/ns_gige_reg.h +++ b/dev/ns_gige_reg.h @@ -304,6 +304,10 @@ #define TANAR_FULL_DUP 0x00000020 #define TANAR_UNUSED 0x00000E1F +/* M5 control register */ +#define M5REG_RESERVED 0xfffffffe +#define M5REG_DEDICATED 0x00000001 + struct ns_desc32 { uint32_t link; /* link field to next descriptor in linked list */ uint32_t bufptr; /* pointer to the first fragment or buffer */ -- cgit v1.2.3