From 8031cd93b53cd3fe17a5a5f21e8e8bd833398e97 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 1 Jun 2005 21:44:00 -0400 Subject: Standardize clock parameter names to 'clock'. Fix description for Bus clock_ratio (no longer a ratio). Add Clock param type (generic Frequency or Latency). cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/beta_cpu/alpha_full_cpu_builder.cc: cpu/simple_cpu/simple_cpu.cc: dev/ide_ctrl.cc: dev/ns_gige.cc: dev/ns_gige.hh: dev/pciconfigall.cc: dev/sinic.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: python/m5/objects/BaseCPU.py: python/m5/objects/BaseCache.py: python/m5/objects/BaseSystem.py: python/m5/objects/Bus.py: python/m5/objects/Ethernet.py: python/m5/objects/Root.py: sim/universe.cc: Standardize clock parameter names to 'clock'. Fix description for Bus clock_ratio (no longer a ratio). python/m5/config.py: Minor tweaks on Frequency/Latency: - added new Clock param type to avoid ambiguities - factored out init code into getLatency() - made RootFrequency *not* a subclass of Frequency so it can't be directly assigned to a Frequency paremeter --HG-- extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506 --- dev/ide_ctrl.cc | 2 +- dev/ns_gige.cc | 12 ++++++------ dev/ns_gige.hh | 6 +++--- dev/pciconfigall.cc | 2 +- dev/sinic.cc | 4 ++-- dev/tsunami_cchip.cc | 2 +- dev/tsunami_io.cc | 2 +- dev/tsunami_pchip.cc | 2 +- dev/uart.cc | 2 +- 9 files changed, 17 insertions(+), 17 deletions(-) (limited to 'dev') diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index ae044427e..35d9020db 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -99,7 +99,7 @@ IdeController::IdeController(Params *p) params()->host_bus, params()->host_bus, 1, true); - pioLatency = params()->pio_latency * params()->host_bus->clockRatio; + pioLatency = params()->pio_latency * params()->host_bus->clockRate; } // setup the disks attached to controller diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 65a162148..637cd7825 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -94,7 +94,7 @@ NSGigE::NSGigE(Params *p) : PciDev(p), ioEnable(false), txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size), txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL), - txXferLen(0), rxXferLen(0), cycleTime(p->cycle_time), + txXferLen(0), rxXferLen(0), clock(p->clock), txState(txIdle), txEnable(false), CTDD(false), txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle), rxEnable(false), CRDD(false), rxPktBytes(0), @@ -115,7 +115,7 @@ NSGigE::NSGigE(Params *p) p->header_bus, this, &NSGigE::cacheAccess); - pioLatency = p->pio_latency * p->header_bus->clockRatio; + pioLatency = p->pio_latency * p->header_bus->clockRate; if (p->payload_bus) dmaInterface = new DMAInterface(name() + ".dma", @@ -132,7 +132,7 @@ NSGigE::NSGigE(Params *p) p->payload_bus, this, &NSGigE::cacheAccess); - pioLatency = p->pio_latency * p->payload_bus->clockRatio; + pioLatency = p->pio_latency * p->payload_bus->clockRate; dmaInterface = new DMAInterface(name() + ".dma", p->payload_bus, @@ -2689,7 +2689,7 @@ REGISTER_SIM_OBJECT("NSGigEInt", NSGigEInt) BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) Param addr; - Param cycle_time; + Param clock; Param tx_delay; Param rx_delay; Param intr_delay; @@ -2723,7 +2723,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(NSGigE) BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(addr, "Device Address"), - INIT_PARAM(cycle_time, "State machine processor frequency"), + INIT_PARAM(clock, "State machine processor frequency"), INIT_PARAM(tx_delay, "Transmit Delay"), INIT_PARAM(rx_delay, "Receive Delay"), INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"), @@ -2769,7 +2769,7 @@ CREATE_SIM_OBJECT(NSGigE) params->deviceNum = pci_dev; params->functionNum = pci_func; - params->cycle_time = cycle_time; + params->clock = clock; params->intr_delay = intr_delay; params->pmem = physmem; params->tx_delay = tx_delay; diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index cbb7185e7..302aa5a89 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -176,8 +176,8 @@ class NSGigE : public PciDev ns_desc rxDescCache; /* state machine cycle time */ - Tick cycleTime; - inline Tick cycles(int numCycles) const { return numCycles * cycleTime; } + Tick clock; + inline Tick cycles(int numCycles) const { return numCycles * clock; } /* tx State Machine */ TxState txState; @@ -328,7 +328,7 @@ class NSGigE : public PciDev HierParams *hier; Bus *header_bus; Bus *payload_bus; - Tick cycle_time; + Tick clock; Tick intr_delay; Tick tx_delay; Tick rx_delay; diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index 2cbd5adc0..fd0732d50 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -59,7 +59,7 @@ PciConfigAll::PciConfigAll(const string &name, pioInterface = newPioInterface(name, hier, bus, this, &PciConfigAll::cacheAccess); pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * bus->clockRatio; + pioLatency = pio_latency * bus->clockRate; } // Make all the pointers to devices null diff --git a/dev/sinic.cc b/dev/sinic.cc index 1f7fceebe..5125a1d68 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -98,7 +98,7 @@ Device::Device(Params *p) pioInterface = newPioInterface(p->name, p->hier, p->io_bus, this, &Device::cacheAccess); - pioLatency = p->pio_latency * p->io_bus->clockRatio; + pioLatency = p->pio_latency * p->io_bus->clockRate; if (p->payload_bus) dmaInterface = new DMAInterface(p->name + ".dma", p->io_bus, @@ -112,7 +112,7 @@ Device::Device(Params *p) pioInterface = newPioInterface(p->name, p->hier, p->payload_bus, this, &Device::cacheAccess); - pioLatency = p->pio_latency * p->payload_bus->clockRatio; + pioLatency = p->pio_latency * p->payload_bus->clockRate; dmaInterface = new DMAInterface(p->name + ".dma", p->payload_bus, p->payload_bus, 1, diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 2fb293fbf..a10dba082 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -59,7 +59,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, pioInterface = newPioInterface(name, hier, bus, this, &TsunamiCChip::cacheAccess); pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * bus->clockRatio; + pioLatency = pio_latency * bus->clockRate; } drir = 0; diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index 895888a09..2e12b41ea 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -175,7 +175,7 @@ TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time, pioInterface = newPioInterface(name, hier, bus, this, &TsunamiIO::cacheAccess); pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * bus->clockRatio; + pioLatency = pio_latency * bus->clockRate; } // set the back pointer from tsunami to myself diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index f846725f9..f8bec77c0 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -65,7 +65,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, pioInterface = newPioInterface(name, hier, bus, this, &TsunamiPChip::cacheAccess); pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * bus->clockRatio; + pioLatency = pio_latency * bus->clockRate; } diff --git a/dev/uart.cc b/dev/uart.cc index caa169a2e..c04a5d066 100644 --- a/dev/uart.cc +++ b/dev/uart.cc @@ -109,7 +109,7 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a, pioInterface = newPioInterface(name, hier, bus, this, &Uart::cacheAccess); pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * bus->clockRatio; + pioLatency = pio_latency * bus->clockRate; } readAddr = 0; -- cgit v1.2.3