From 2939a7089ad89e38b24f96143dbd3c4292ac0287 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Feb 2006 00:16:44 -0500 Subject: byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions. arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: Added the endianness namespace. This may change. cpu/exec_context.hh: Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution. cpu/o3/alpha_cpu.hh: Forced LittleEndianness, for lack of a better solution. cpu/o3/alpha_cpu_impl.hh: Cleared away some commented out code. cpu/o3/fetch_impl.hh: Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution. cpu/simple/cpu.cc: Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine. dev/disk_image.cc: Changed the include path of byteswap.hh kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution. sim/system.cc: Forced LittleEndianness for lack of a better solution. --HG-- extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206 --- dev/disk_image.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'dev') diff --git a/dev/disk_image.cc b/dev/disk_image.cc index 106723c55..447c54697 100644 --- a/dev/disk_image.cc +++ b/dev/disk_image.cc @@ -46,7 +46,7 @@ #include "dev/disk_image.hh" #include "sim/builder.hh" #include "sim/sim_exit.hh" -#include "targetarch/byte_swap.hh" +#include "sim/byteswap.hh" using namespace std; -- cgit v1.2.3 From 2c5e03550adcd1348cc1d6f3c00af77cbf99c5ce Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 12 Feb 2006 12:40:58 -0500 Subject: Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh. SConscript: Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh targetarch/isa_traits.hh is now included through arch/isa_traits.hh vptr.hh was removed from targetarch, and moved to sim arch/alpha/pseudo_inst.cc: Moved vptr.hh from targetarch to sim base/loader/object_file.hh: base/loader/symtab.hh: cpu/base.hh: dev/ide_disk.cc: Changed the include of isa_traits.hh from targetarch to arch cpu/static_inst.hh: dev/platform.hh: dev/simple_disk.hh: kern/tru64/dump_mbuf.cc: kern/tru64/mbuf.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/process.hh: sim/syscall_emul.hh: Changed the include of isa_traits.hh from targetarch to arch. kern/linux/linux_threadinfo.hh: Changed the include of vptr.hh from targetarch to sim. sim/byteswap.hh: Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t) sim/vptr.hh: Fixed the assert in the equals operator. Changed the AlphaISA namespace reference to TheISA. Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures. Added an include of arch/isa_traits.hh so that TheISA would be defined. --HG-- extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f --- dev/ide_disk.cc | 2 +- dev/platform.hh | 2 +- dev/simple_disk.hh | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'dev') diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc index ea8f151c0..9d8bb8825 100644 --- a/dev/ide_disk.cc +++ b/dev/ide_disk.cc @@ -50,7 +50,7 @@ #include "sim/builder.hh" #include "sim/sim_object.hh" #include "sim/root.hh" -#include "targetarch/isa_traits.hh" +#include "arch/isa_traits.hh" using namespace std; diff --git a/dev/platform.hh b/dev/platform.hh index ee9c72617..1ee645454 100644 --- a/dev/platform.hh +++ b/dev/platform.hh @@ -35,7 +35,7 @@ #define __DEV_PLATFORM_HH__ #include "sim/sim_object.hh" -#include "targetarch/isa_traits.hh" +#include "arch/isa_traits.hh" class PciConfigAll; class IntrControl; diff --git a/dev/simple_disk.hh b/dev/simple_disk.hh index 006155168..6560e15c2 100644 --- a/dev/simple_disk.hh +++ b/dev/simple_disk.hh @@ -34,7 +34,7 @@ #define __DEV_SIMPLE_DISK_HH__ #include "sim/sim_object.hh" -#include "targetarch/isa_traits.hh" +#include "arch/isa_traits.hh" class DiskImage; class PhysicalMemory; -- cgit v1.2.3 From 10c79efe556697ebbed74c82214b5505b405da5b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 16 Feb 2006 01:22:51 -0500 Subject: Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA. SConscript: The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away. arch/alpha/alpha_memory.cc: Changed Fault to Fault * and took the underscores out of fault names. arch/alpha/alpha_memory.hh: Changed Fault to Fault *. Also, added an include for the alpha faults. arch/alpha/ev5.cc: Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names. arch/alpha/isa/decoder.isa: Changed Fault to Fault * and took the underscores out fault names. arch/alpha/isa/fp.isa: Changed Fault to Fault *, and took the underscores out of fault names. arch/alpha/isa/main.isa: Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files. arch/alpha/isa/mem.isa: Changed Fault to Fault * and removed underscores from fault names. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: cpu/exec_context.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: dev/alpha_console.cc: dev/ide_ctrl.cc: dev/isa_fake.cc: dev/pciconfigall.cc: dev/pcidev.cc: dev/pcidev.hh: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Changed Fault to Fault *, and removed underscores from fault names. arch/alpha/isa_traits.hh: Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed. cpu/base_dyn_inst.cc: Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault. cpu/base_dyn_inst.hh: Changed Fault to Fault * and took the underscores out of the fault names. cpu/exec_context.cc: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/fetch.hh: dev/alpha_console.hh: dev/baddev.hh: dev/ide_ctrl.hh: dev/isa_fake.hh: dev/ns_gige.hh: dev/pciconfigall.hh: dev/sinic.hh: dev/tsunami_cchip.hh: dev/tsunami_io.hh: dev/tsunami_pchip.hh: dev/uart.hh: dev/uart8250.hh: Changed Fault to Fault *. cpu/o3/alpha_cpu.hh: Changed Fault to Fault *, removed underscores from fault names. cpu/o3/alpha_cpu_impl.hh: Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away. cpu/o3/commit_impl.hh: cpu/o3/fetch_impl.hh: dev/baddev.cc: Changed Fault to Fault *, and removed underscores from the fault names. cpu/o3/regfile.hh: Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names. cpu/simple/cpu.hh: Changed Fault to Fault * dev/ns_gige.cc: Changed Fault to Fault *, and removdd underscores from fault names. dev/sinic.cc: Changed Fault to Fault *, and removed the underscores from fault names. dev/uart8250.cc: Chanted Fault to Fault *, and removed underscores from fault names. kern/kernel_stats.cc: Removed underscores from fault names, and from NumFaults. kern/kernel_stats.hh: Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally. sim/faults.cc: This allocates the system wide faults. sim/faults.hh: This declares the system wide faults. sim/syscall_emul.cc: sim/syscall_emul.hh: Removed the underscores from fault names. --HG-- rename : arch/alpha/faults.cc => sim/faults.cc rename : arch/alpha/faults.hh => sim/faults.hh extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d --- dev/alpha_console.cc | 14 +++++------ dev/alpha_console.hh | 4 +-- dev/baddev.cc | 8 +++--- dev/baddev.hh | 4 +-- dev/ide_ctrl.cc | 14 +++++------ dev/ide_ctrl.hh | 4 +-- dev/isa_fake.cc | 16 ++++++------ dev/isa_fake.hh | 4 +-- dev/ns_gige.cc | 14 +++++------ dev/ns_gige.hh | 4 +-- dev/pciconfigall.cc | 18 +++++++------- dev/pciconfigall.hh | 4 +-- dev/pcidev.cc | 32 ++++++++++++------------ dev/pcidev.hh | 40 +++++++++++++++--------------- dev/sinic.cc | 28 ++++++++++----------- dev/sinic.hh | 10 ++++---- dev/tsunami_cchip.cc | 68 +++++++++++++++++++++++++------------------------- dev/tsunami_cchip.hh | 4 +-- dev/tsunami_io.cc | 70 ++++++++++++++++++++++++++-------------------------- dev/tsunami_io.hh | 4 +-- dev/tsunami_pchip.cc | 70 ++++++++++++++++++++++++++-------------------------- dev/tsunami_pchip.hh | 4 +-- dev/uart.hh | 4 +-- dev/uart8250.cc | 8 +++--- dev/uart8250.hh | 4 +-- 25 files changed, 227 insertions(+), 227 deletions(-) (limited to 'dev') diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 61b444628..38fbbdef0 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -99,7 +99,7 @@ AlphaConsole::startup() alphaAccess->intrClockFrequency = platform->intrFrequency(); } -Fault +Fault * AlphaConsole::read(MemReqPtr &req, uint8_t *data) { memset(data, 0, req->size); @@ -183,13 +183,13 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) } break; default: - return Machine_Check_Fault; + return MachineCheckFault; } - return No_Fault; + return NoFault; } -Fault +Fault * AlphaConsole::write(MemReqPtr &req, const uint8_t *data) { uint64_t val; @@ -203,7 +203,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) val = *(uint64_t *)data; break; default: - return Machine_Check_Fault; + return MachineCheckFault; } Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); @@ -256,10 +256,10 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) break; default: - return Machine_Check_Fault; + return MachineCheckFault; } - return No_Fault; + return NoFault; } Tick diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh index 74ad795f0..75f0a3a67 100644 --- a/dev/alpha_console.hh +++ b/dev/alpha_console.hh @@ -110,8 +110,8 @@ class AlphaConsole : public PioDevice /** * memory mapped reads and writes */ - virtual Fault read(MemReqPtr &req, uint8_t *data); - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); /** * standard serialization routines for checkpointing diff --git a/dev/baddev.cc b/dev/baddev.cc index 52c538707..b6ca919e4 100644 --- a/dev/baddev.cc +++ b/dev/baddev.cc @@ -61,19 +61,19 @@ BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu, } -Fault +Fault * BadDevice::read(MemReqPtr &req, uint8_t *data) { panic("Device %s not imlpmented\n", devname); - return No_Fault; + return NoFault; } -Fault +Fault * BadDevice::write(MemReqPtr &req, const uint8_t *data) { panic("Device %s not imlpmented\n", devname); - return No_Fault; + return NoFault; } Tick diff --git a/dev/baddev.hh b/dev/baddev.hh index c2a204c05..b7b67e31a 100644 --- a/dev/baddev.hh +++ b/dev/baddev.hh @@ -71,7 +71,7 @@ class BadDevice : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); /** * On a write event we just panic aand hopefully print a @@ -80,7 +80,7 @@ class BadDevice : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); /** * Return how long this access will take. diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index 1279efc82..a5cb0dfd8 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -390,7 +390,7 @@ IdeController::writeConfig(int offset, int size, const uint8_t *data) } } -Fault +Fault * IdeController::read(MemReqPtr &req, uint8_t *data) { Addr offset; @@ -401,7 +401,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data) parseAddr(req->paddr, offset, channel, reg_type); if (!io_enabled) - return No_Fault; + return NoFault; switch (reg_type) { case BMI_BLOCK: @@ -457,10 +457,10 @@ IdeController::read(MemReqPtr &req, uint8_t *data) DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n", offset, req->size, *(uint32_t*)data); - return No_Fault; + return NoFault; } -Fault +Fault * IdeController::write(MemReqPtr &req, const uint8_t *data) { Addr offset; @@ -472,12 +472,12 @@ IdeController::write(MemReqPtr &req, const uint8_t *data) parseAddr(req->paddr, offset, channel, reg_type); if (!io_enabled) - return No_Fault; + return NoFault; switch (reg_type) { case BMI_BLOCK: if (!bm_enabled) - return No_Fault; + return NoFault; switch (offset) { // Bus master IDE command register @@ -627,7 +627,7 @@ IdeController::write(MemReqPtr &req, const uint8_t *data) DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n", offset, req->size, *(uint32_t*)data); - return No_Fault; + return NoFault; } //// diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh index 0fbaf9207..72523f57c 100644 --- a/dev/ide_ctrl.hh +++ b/dev/ide_ctrl.hh @@ -213,7 +213,7 @@ class IdeController : public PciDev * @param data Return the field read. * @return The fault condition of the access. */ - virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); /** * Write to the mmapped I/O control registers. @@ -221,7 +221,7 @@ class IdeController : public PciDev * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); /** * Serialize this object to the given output stream. diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc index e2802eaa9..93c9eedbf 100644 --- a/dev/isa_fake.cc +++ b/dev/isa_fake.cc @@ -59,7 +59,7 @@ IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu, } } -Fault +Fault * IsaFake::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "read va=%#x size=%d\n", @@ -73,26 +73,26 @@ IsaFake::read(MemReqPtr &req, uint8_t *data) case sizeof(uint64_t): *(uint64_t*)data = 0xFFFFFFFFFFFFFFFFULL; - return No_Fault; + return NoFault; case sizeof(uint32_t): *(uint32_t*)data = 0xFFFFFFFF; - return No_Fault; + return NoFault; case sizeof(uint16_t): *(uint16_t*)data = 0xFFFF; - return No_Fault; + return NoFault; case sizeof(uint8_t): *(uint8_t*)data = 0xFF; - return No_Fault; + return NoFault; default: panic("invalid access size(?) for PCI configspace!\n"); } DPRINTFN("Isa FakeSMC ERROR: read daddr=%#x size=%d\n", daddr, req->size); - return No_Fault; + return NoFault; } -Fault +Fault * IsaFake::write(MemReqPtr &req, const uint8_t *data) { DPRINTF(Tsunami, "write - va=%#x size=%d \n", @@ -100,7 +100,7 @@ IsaFake::write(MemReqPtr &req, const uint8_t *data) //:Addr daddr = (req->paddr & addr_mask) >> 6; - return No_Fault; + return NoFault; } Tick diff --git a/dev/isa_fake.hh b/dev/isa_fake.hh index 290b24b54..60ca5f90a 100644 --- a/dev/isa_fake.hh +++ b/dev/isa_fake.hh @@ -65,14 +65,14 @@ class IsaFake : public PioDevice * @param req The memory request. * @param data Where to put the data. */ - virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); /** * All writes are simply ignored. * @param req The memory request. * @param data the data to not write. */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); /** * Return how long this access will take. diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 9010850ab..c28615438 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -558,7 +558,7 @@ NSGigE::writeConfig(int offset, int size, const uint8_t* data) * This reads the device registers, which are detailed in the NS83820 * spec sheet */ -Fault +Fault * NSGigE::read(MemReqPtr &req, uint8_t *data) { assert(ioEnable); @@ -575,14 +575,14 @@ NSGigE::read(MemReqPtr &req, uint8_t *data) panic("Accessing reserved register"); } else if (daddr > RESERVED && daddr <= 0x3FC) { readConfig(daddr & 0xff, req->size, data); - return No_Fault; + return NoFault; } else if (daddr >= MIB_START && daddr <= MIB_END) { // don't implement all the MIB's. hopefully the kernel // doesn't actually DEPEND upon their values // MIB are just hardware stats keepers uint32_t ® = *(uint32_t *) data; reg = 0; - return No_Fault; + return NoFault; } else if (daddr > 0x3FC) panic("Something is messed up!\n"); @@ -784,10 +784,10 @@ NSGigE::read(MemReqPtr &req, uint8_t *data) daddr, req->size); } - return No_Fault; + return NoFault; } -Fault +Fault * NSGigE::write(MemReqPtr &req, const uint8_t *data) { assert(ioEnable); @@ -800,7 +800,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data) panic("Accessing reserved register"); } else if (daddr > RESERVED && daddr <= 0x3FC) { writeConfig(daddr & 0xff, req->size, data); - return No_Fault; + return NoFault; } else if (daddr > 0x3FC) panic("Something is messed up!\n"); @@ -1203,7 +1203,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data) panic("Invalid Request Size"); } - return No_Fault; + return NoFault; } void diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index ade7e32e6..b65626b7b 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -408,8 +408,8 @@ class NSGigE : public PciDev virtual void writeConfig(int offset, int size, const uint8_t *data); virtual void readConfig(int offset, int size, uint8_t *data); - virtual Fault read(MemReqPtr &req, uint8_t *data); - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); bool cpuIntrPending() const; void cpuIntrAck() { cpuIntrClear(); } diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index 396e130af..1175172c4 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -95,7 +95,7 @@ PciConfigAll::startup() } -Fault +Fault * PciConfigAll::read(MemReqPtr &req, uint8_t *data) { @@ -112,16 +112,16 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data) switch (req->size) { // case sizeof(uint64_t): // *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF; - // return No_Fault; + // return NoFault; case sizeof(uint32_t): *(uint32_t*)data = 0xFFFFFFFF; - return No_Fault; + return NoFault; case sizeof(uint16_t): *(uint16_t*)data = 0xFFFF; - return No_Fault; + return NoFault; case sizeof(uint8_t): *(uint8_t*)data = 0xFF; - return No_Fault; + return NoFault; default: panic("invalid access size(?) for PCI configspace!\n"); } @@ -131,7 +131,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data) case sizeof(uint16_t): case sizeof(uint8_t): devices[device][func]->readConfig(reg, req->size, data); - return No_Fault; + return NoFault; default: panic("invalid access size(?) for PCI configspace!\n"); } @@ -140,10 +140,10 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data) DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n", daddr, req->size); - return No_Fault; + return NoFault; } -Fault +Fault * PciConfigAll::write(MemReqPtr &req, const uint8_t *data) { Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); @@ -164,7 +164,7 @@ PciConfigAll::write(MemReqPtr &req, const uint8_t *data) devices[device][func]->writeConfig(reg, req->size, data); - return No_Fault; + return NoFault; } void diff --git a/dev/pciconfigall.hh b/dev/pciconfigall.hh index c6a0241d8..6df033286 100644 --- a/dev/pciconfigall.hh +++ b/dev/pciconfigall.hh @@ -103,7 +103,7 @@ class PciConfigAll : public PioDevice * @param data Return the field read. * @return The fault condition of the access. */ - virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); /** * Write to PCI config spcae. If the device does not exit the simulator @@ -114,7 +114,7 @@ class PciConfigAll : public PioDevice * @return The fault condition of the access. */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); /** * Start up function to check if more than one person is using an interrupt line diff --git a/dev/pcidev.cc b/dev/pcidev.cc index 1d9ea137d..c469e716a 100644 --- a/dev/pcidev.cc +++ b/dev/pcidev.cc @@ -70,59 +70,59 @@ PciDev::PciDev(Params *p) p->configSpace->registerDevice(p->deviceNum, p->functionNum, this); } -Fault +Fault * PciDev::read(MemReqPtr &req, uint8_t *data) -{ return No_Fault; } +{ return NoFault; } -Fault +Fault * PciDev::write(MemReqPtr &req, const uint8_t *data) -{ return No_Fault; } +{ return NoFault; } -Fault +Fault * PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault +Fault * PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault +Fault * PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault +Fault * PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault +Fault * PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault +Fault * PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault +Fault * PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault +Fault * PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault +Fault * PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault +Fault * PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault +Fault * PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault +Fault * PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } diff --git a/dev/pcidev.hh b/dev/pcidev.hh index efc805b3f..c8d9685c1 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -189,37 +189,37 @@ class PciDev : public DmaDevice */ PciDev(Params *params); - virtual Fault read(MemReqPtr &req, uint8_t *data); - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); public: /** * Implement the read/write as BAR accesses */ - Fault readBar(MemReqPtr &req, uint8_t *data); - Fault writeBar(MemReqPtr &req, const uint8_t *data); + Fault * readBar(MemReqPtr &req, uint8_t *data); + Fault * writeBar(MemReqPtr &req, const uint8_t *data); public: /** * Read from a specific BAR */ - virtual Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault readBar1(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault readBar2(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault readBar3(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault readBar4(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault readBar5(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault * readBar1(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault * readBar2(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault * readBar3(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault * readBar4(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault * readBar5(MemReqPtr &req, Addr daddr, uint8_t *data); public: /** * Write to a specific BAR */ - virtual Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault * writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault * writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault * writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault * writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault * writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data); public: /** @@ -257,7 +257,7 @@ class PciDev : public DmaDevice virtual void unserialize(Checkpoint *cp, const std::string §ion); }; -inline Fault +inline Fault * PciDev::readBar(MemReqPtr &req, uint8_t *data) { if (isBAR(req->paddr, 0)) @@ -272,10 +272,10 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data) return readBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return readBar5(req, req->paddr - BARAddrs[5], data); - return Machine_Check_Fault; + return MachineCheckFault; } -inline Fault +inline Fault * PciDev::writeBar(MemReqPtr &req, const uint8_t *data) { if (isBAR(req->paddr, 0)) @@ -290,7 +290,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data) return writeBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return writeBar5(req, req->paddr - BARAddrs[5], data); - return Machine_Check_Fault; + return MachineCheckFault; } #endif // __DEV_PCIDEV_HH__ diff --git a/dev/sinic.cc b/dev/sinic.cc index 69239df32..e79f80678 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -361,23 +361,23 @@ Device::prepareWrite(int cpu, int index) /** * I/O read of device register */ -Fault +Fault * Device::read(MemReqPtr &req, uint8_t *data) { assert(config.command & PCI_CMD_MSE); - Fault fault = readBar(req, data); + Fault * fault = readBar(req, data); - if (fault == Machine_Check_Fault) { + if (fault == MachineCheckFault) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return Machine_Check_Fault; + return MachineCheckFault; } return fault; } -Fault +Fault * Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) { int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; @@ -421,13 +421,13 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) if (raddr == Regs::IntrStatus) devIntrClear(); - return No_Fault; + return NoFault; } /** * IPR read of device register */ -Fault +Fault * Device::iprRead(Addr daddr, int cpu, uint64_t &result) { if (!regValid(daddr)) @@ -451,29 +451,29 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result) DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n", info.name, cpu, result); - return No_Fault; + return NoFault; } /** * I/O write of device register */ -Fault +Fault * Device::write(MemReqPtr &req, const uint8_t *data) { assert(config.command & PCI_CMD_MSE); - Fault fault = writeBar(req, data); + Fault * fault = writeBar(req, data); - if (fault == Machine_Check_Fault) { + if (fault == MachineCheckFault) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return Machine_Check_Fault; + return MachineCheckFault; } return fault; } -Fault +Fault * Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) { int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; @@ -508,7 +508,7 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) if (!pioDelayWrite || !info.delay_write) regWrite(daddr, cpu, data); - return No_Fault; + return NoFault; } void diff --git a/dev/sinic.hh b/dev/sinic.hh index af2f109a4..7935a7cdc 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -271,15 +271,15 @@ class Device : public Base * Memory Interface */ public: - virtual Fault read(MemReqPtr &req, uint8_t *data); - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); void prepareIO(int cpu, int index); void prepareRead(int cpu, int index); void prepareWrite(int cpu, int index); - Fault iprRead(Addr daddr, int cpu, uint64_t &result); - Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); - Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); + Fault * iprRead(Addr daddr, int cpu, uint64_t &result); + Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); + Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); void regWrite(Addr daddr, int cpu, const uint8_t *data); Tick cacheAccess(MemReqPtr &req); diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 2287a2a3d..4cda9ec36 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -76,7 +76,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, tsunami->cchip = this; } -Fault +Fault * TsunamiCChip::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size); @@ -92,81 +92,81 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) if (daddr & TSDEV_CC_BDIMS) { *(uint64_t*)data = dim[(daddr >> 4) & 0x3F]; - return No_Fault; + return NoFault; } if (daddr & TSDEV_CC_BDIRS) { *(uint64_t*)data = dir[(daddr >> 4) & 0x3F]; - return No_Fault; + return NoFault; } switch(regnum) { case TSDEV_CC_CSR: *(uint64_t*)data = 0x0; - return No_Fault; + return NoFault; case TSDEV_CC_MTR: panic("TSDEV_CC_MTR not implemeted\n"); - return No_Fault; + return NoFault; case TSDEV_CC_MISC: *(uint64_t*)data = (ipint << 8) & 0xF | (itint << 4) & 0xF | (xc->cpu_id & 0x3); - return No_Fault; + return NoFault; case TSDEV_CC_AAR0: case TSDEV_CC_AAR1: case TSDEV_CC_AAR2: case TSDEV_CC_AAR3: *(uint64_t*)data = 0; - return No_Fault; + return NoFault; case TSDEV_CC_DIM0: *(uint64_t*)data = dim[0]; - return No_Fault; + return NoFault; case TSDEV_CC_DIM1: *(uint64_t*)data = dim[1]; - return No_Fault; + return NoFault; case TSDEV_CC_DIM2: *(uint64_t*)data = dim[2]; - return No_Fault; + return NoFault; case TSDEV_CC_DIM3: *(uint64_t*)data = dim[3]; - return No_Fault; + return NoFault; case TSDEV_CC_DIR0: *(uint64_t*)data = dir[0]; - return No_Fault; + return NoFault; case TSDEV_CC_DIR1: *(uint64_t*)data = dir[1]; - return No_Fault; + return NoFault; case TSDEV_CC_DIR2: *(uint64_t*)data = dir[2]; - return No_Fault; + return NoFault; case TSDEV_CC_DIR3: *(uint64_t*)data = dir[3]; - return No_Fault; + return NoFault; case TSDEV_CC_DRIR: *(uint64_t*)data = drir; - return No_Fault; + return NoFault; case TSDEV_CC_PRBEN: panic("TSDEV_CC_PRBEN not implemented\n"); - return No_Fault; + return NoFault; case TSDEV_CC_IIC0: case TSDEV_CC_IIC1: case TSDEV_CC_IIC2: case TSDEV_CC_IIC3: panic("TSDEV_CC_IICx not implemented\n"); - return No_Fault; + return NoFault; case TSDEV_CC_MPR0: case TSDEV_CC_MPR1: case TSDEV_CC_MPR2: case TSDEV_CC_MPR3: panic("TSDEV_CC_MPRx not implemented\n"); - return No_Fault; + return NoFault; case TSDEV_CC_IPIR: *(uint64_t*)data = ipint; - return No_Fault; + return NoFault; case TSDEV_CC_ITIR: *(uint64_t*)data = itint; - return No_Fault; + return NoFault; default: panic("default in cchip read reached, accessing 0x%x\n"); } // uint64_t @@ -179,7 +179,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) *(uint32_t*)data = drir; } else panic("invalid access size(?) for tsunami register!\n"); - return No_Fault; + return NoFault; case sizeof(uint16_t): case sizeof(uint8_t): default: @@ -187,10 +187,10 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) } DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum, req->size); - return No_Fault; + return NoFault; } -Fault +Fault * TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) { DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n", @@ -243,16 +243,16 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) } } - return No_Fault; + return NoFault; } switch(regnum) { case TSDEV_CC_CSR: panic("TSDEV_CC_CSR write\n"); - return No_Fault; + return NoFault; case TSDEV_CC_MTR: panic("TSDEV_CC_MTR write not implemented\n"); - return No_Fault; + return NoFault; case TSDEV_CC_MISC: uint64_t ipreq; ipreq = (*(uint64_t*)data >> 12) & 0xF; @@ -285,13 +285,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) if(!supportedWrite) panic("TSDEV_CC_MISC write not implemented\n"); - return No_Fault; + return NoFault; case TSDEV_CC_AAR0: case TSDEV_CC_AAR1: case TSDEV_CC_AAR2: case TSDEV_CC_AAR3: panic("TSDEV_CC_AARx write not implemeted\n"); - return No_Fault; + return NoFault; case TSDEV_CC_DIM0: case TSDEV_CC_DIM1: case TSDEV_CC_DIM2: @@ -341,7 +341,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) } } - return No_Fault; + return NoFault; case TSDEV_CC_DIR0: case TSDEV_CC_DIR1: case TSDEV_CC_DIR2: @@ -363,13 +363,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) panic("TSDEV_CC_MPRx write not implemented\n"); case TSDEV_CC_IPIR: clearIPI(*(uint64_t*)data); - return No_Fault; + return NoFault; case TSDEV_CC_ITIR: clearITI(*(uint64_t*)data); - return No_Fault; + return NoFault; case TSDEV_CC_IPIQ: reqIPI(*(uint64_t*)data); - return No_Fault; + return NoFault; default: panic("default in cchip read reached, accessing 0x%x\n"); } @@ -384,7 +384,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); - return No_Fault; + return NoFault; } void diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh index d88ad375f..dadbdb0e3 100644 --- a/dev/tsunami_cchip.hh +++ b/dev/tsunami_cchip.hh @@ -105,7 +105,7 @@ class TsunamiCChip : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); /** @@ -114,7 +114,7 @@ class TsunamiCChip : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); /** * post an RTC interrupt to the CPU diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index 724a5bfb9..0d0d27570 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -444,7 +444,7 @@ TsunamiIO::frequency() const return Clock::Frequency / clockInterval; } -Fault +Fault * TsunamiIO::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", @@ -459,38 +459,38 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) // PIC1 mask read case TSDEV_PIC1_MASK: *(uint8_t*)data = ~mask1; - return No_Fault; + return NoFault; case TSDEV_PIC2_MASK: *(uint8_t*)data = ~mask2; - return No_Fault; + return NoFault; case TSDEV_PIC1_ISR: // !!! If this is modified 64bit case needs to be too // Pal code has to do a 64 bit physical read because there is // no load physical byte instruction *(uint8_t*)data = picr; - return No_Fault; + return NoFault; case TSDEV_PIC2_ISR: // PIC2 not implemnted... just return 0 *(uint8_t*)data = 0x00; - return No_Fault; + return NoFault; case TSDEV_TMR0_DATA: pitimer.counter0.read(data); - return No_Fault; + return NoFault; case TSDEV_TMR1_DATA: pitimer.counter1.read(data); - return No_Fault; + return NoFault; case TSDEV_TMR2_DATA: pitimer.counter2.read(data); - return No_Fault; + return NoFault; case TSDEV_RTC_DATA: rtc.readData(data); - return No_Fault; + return NoFault; case TSDEV_CTRL_PORTB: if (pitimer.counter2.outputHigh()) *data = PORTB_SPKR_HIGH; else *data = 0x00; - return No_Fault; + return NoFault; default: panic("I/O Read - va%#x size %d\n", req->vaddr, req->size); } @@ -506,7 +506,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) // Pal code has to do a 64 bit physical read because there is // no load physical byte instruction *(uint64_t*)data = (uint64_t)picr; - return No_Fault; + return NoFault; default: panic("I/O Read - invalid size - va %#x size %d\n", req->vaddr, req->size); @@ -518,10 +518,10 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) } panic("I/O Read - va%#x size %d\n", req->vaddr, req->size); - return No_Fault; + return NoFault; } -Fault +Fault * TsunamiIO::write(MemReqPtr &req, const uint8_t *data) { @@ -550,63 +550,63 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data) tsunami->cchip->clearDRIR(55); DPRINTF(Tsunami, "clearing pic interrupt\n"); } - return No_Fault; + return NoFault; case TSDEV_PIC2_MASK: mask2 = *(uint8_t*)data; //PIC2 Not implemented to interrupt - return No_Fault; + return NoFault; case TSDEV_PIC1_ACK: // clear the interrupt on the PIC picr &= ~(1 << (*(uint8_t*)data & 0xF)); if (!(picr & mask1)) tsunami->cchip->clearDRIR(55); - return No_Fault; + return NoFault; case TSDEV_DMA1_CMND: - return No_Fault; + return NoFault; case TSDEV_DMA2_CMND: - return No_Fault; + return NoFault; case TSDEV_DMA1_MMASK: - return No_Fault; + return NoFault; case TSDEV_DMA2_MMASK: - return No_Fault; + return NoFault; case TSDEV_PIC2_ACK: - return No_Fault; + return NoFault; case TSDEV_DMA1_RESET: - return No_Fault; + return NoFault; case TSDEV_DMA2_RESET: - return No_Fault; + return NoFault; case TSDEV_DMA1_MODE: mode1 = *(uint8_t*)data; - return No_Fault; + return NoFault; case TSDEV_DMA2_MODE: mode2 = *(uint8_t*)data; - return No_Fault; + return NoFault; case TSDEV_DMA1_MASK: case TSDEV_DMA2_MASK: - return No_Fault; + return NoFault; case TSDEV_TMR0_DATA: pitimer.counter0.write(data); - return No_Fault; + return NoFault; case TSDEV_TMR1_DATA: pitimer.counter1.write(data); - return No_Fault; + return NoFault; case TSDEV_TMR2_DATA: pitimer.counter2.write(data); - return No_Fault; + return NoFault; case TSDEV_TMR_CTRL: pitimer.writeControl(data); - return No_Fault; + return NoFault; case TSDEV_RTC_ADDR: rtc.writeAddr(data); - return No_Fault; + return NoFault; case TSDEV_KBD: - return No_Fault; + return NoFault; case TSDEV_RTC_DATA: rtc.writeData(data); - return No_Fault; + return NoFault; case TSDEV_CTRL_PORTB: // System Control Port B not implemented - return No_Fault; + return NoFault; default: panic("I/O Write - va%#x size %d data %#x\n", req->vaddr, req->size, (int)*data); } @@ -619,7 +619,7 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data) } - return No_Fault; + return NoFault; } void diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh index b024ecd14..3b26ebfaa 100644 --- a/dev/tsunami_io.hh +++ b/dev/tsunami_io.hh @@ -330,7 +330,7 @@ class TsunamiIO : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); /** * Process a write to one of the devices we emulate. @@ -338,7 +338,7 @@ class TsunamiIO : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); /** * Post an PIC interrupt to the CPU via the CChip diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index e61137170..a4c04a79f 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -76,7 +76,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, tsunami->pchip = this; } -Fault +Fault * TsunamiPChip::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "read va=%#x size=%d\n", @@ -90,60 +90,60 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data) switch(daddr) { case TSDEV_PC_WSBA0: *(uint64_t*)data = wsba[0]; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA1: *(uint64_t*)data = wsba[1]; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA2: *(uint64_t*)data = wsba[2]; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA3: *(uint64_t*)data = wsba[3]; - return No_Fault; + return NoFault; case TSDEV_PC_WSM0: *(uint64_t*)data = wsm[0]; - return No_Fault; + return NoFault; case TSDEV_PC_WSM1: *(uint64_t*)data = wsm[1]; - return No_Fault; + return NoFault; case TSDEV_PC_WSM2: *(uint64_t*)data = wsm[2]; - return No_Fault; + return NoFault; case TSDEV_PC_WSM3: *(uint64_t*)data = wsm[3]; - return No_Fault; + return NoFault; case TSDEV_PC_TBA0: *(uint64_t*)data = tba[0]; - return No_Fault; + return NoFault; case TSDEV_PC_TBA1: *(uint64_t*)data = tba[1]; - return No_Fault; + return NoFault; case TSDEV_PC_TBA2: *(uint64_t*)data = tba[2]; - return No_Fault; + return NoFault; case TSDEV_PC_TBA3: *(uint64_t*)data = tba[3]; - return No_Fault; + return NoFault; case TSDEV_PC_PCTL: *(uint64_t*)data = pctl; - return No_Fault; + return NoFault; case TSDEV_PC_PLAT: panic("PC_PLAT not implemented\n"); case TSDEV_PC_RES: panic("PC_RES not implemented\n"); case TSDEV_PC_PERROR: *(uint64_t*)data = 0x00; - return No_Fault; + return NoFault; case TSDEV_PC_PERRMASK: *(uint64_t*)data = 0x00; - return No_Fault; + return NoFault; case TSDEV_PC_PERRSET: panic("PC_PERRSET not implemented\n"); case TSDEV_PC_TLBIV: panic("PC_TLBIV not implemented\n"); case TSDEV_PC_TLBIA: *(uint64_t*)data = 0x00; // shouldn't be readable, but linux - return No_Fault; + return NoFault; case TSDEV_PC_PMONCTL: panic("PC_PMONCTL not implemented\n"); case TSDEV_PC_PMONCNT: @@ -162,10 +162,10 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data) } DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); - return No_Fault; + return NoFault; } -Fault +Fault * TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) { DPRINTF(Tsunami, "write - va=%#x size=%d \n", @@ -179,49 +179,49 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) switch(daddr) { case TSDEV_PC_WSBA0: wsba[0] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA1: wsba[1] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA2: wsba[2] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA3: wsba[3] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSM0: wsm[0] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSM1: wsm[1] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSM2: wsm[2] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSM3: wsm[3] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_TBA0: tba[0] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_TBA1: tba[1] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_TBA2: tba[2] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_TBA3: tba[3] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_PCTL: pctl = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_PLAT: panic("PC_PLAT not implemented\n"); case TSDEV_PC_RES: panic("PC_RES not implemented\n"); case TSDEV_PC_PERROR: - return No_Fault; + return NoFault; case TSDEV_PC_PERRMASK: panic("PC_PERRMASK not implemented\n"); case TSDEV_PC_PERRSET: @@ -229,7 +229,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) case TSDEV_PC_TLBIV: panic("PC_TLBIV not implemented\n"); case TSDEV_PC_TLBIA: - return No_Fault; // value ignored, supposted to invalidate SG TLB + return NoFault; // value ignored, supposted to invalidate SG TLB case TSDEV_PC_PMONCTL: panic("PC_PMONCTL not implemented\n"); case TSDEV_PC_PMONCNT: @@ -249,7 +249,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); - return No_Fault; + return NoFault; } #define DMA_ADDR_MASK ULL(0x3ffffffff) diff --git a/dev/tsunami_pchip.hh b/dev/tsunami_pchip.hh index c1d95431b..ff888bea1 100644 --- a/dev/tsunami_pchip.hh +++ b/dev/tsunami_pchip.hh @@ -99,7 +99,7 @@ class TsunamiPChip : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); /** * Process a write to the PChip. @@ -107,7 +107,7 @@ class TsunamiPChip : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); /** * Serialize this object to the given output stream. diff --git a/dev/uart.hh b/dev/uart.hh index 145b9ca9e..96c22025c 100644 --- a/dev/uart.hh +++ b/dev/uart.hh @@ -57,8 +57,8 @@ class Uart : public PioDevice Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p); - virtual Fault read(MemReqPtr &req, uint8_t *data) = 0; - virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0; + virtual Fault * read(MemReqPtr &req, uint8_t *data) = 0; + virtual Fault * write(MemReqPtr &req, const uint8_t *data) = 0; /** diff --git a/dev/uart8250.cc b/dev/uart8250.cc index 71f429069..a2e782189 100644 --- a/dev/uart8250.cc +++ b/dev/uart8250.cc @@ -111,7 +111,7 @@ Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu, } -Fault +Fault * Uart8250::read(MemReqPtr &req, uint8_t *data) { Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); @@ -183,11 +183,11 @@ Uart8250::read(MemReqPtr &req, uint8_t *data) break; } - return No_Fault; + return NoFault; } -Fault +Fault * Uart8250::write(MemReqPtr &req, const uint8_t *data) { Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); @@ -255,7 +255,7 @@ Uart8250::write(MemReqPtr &req, const uint8_t *data) panic("Tried to access a UART port that doesn't exist\n"); break; } - return No_Fault; + return NoFault; } void diff --git a/dev/uart8250.hh b/dev/uart8250.hh index 88abf8e24..a0e2d344a 100644 --- a/dev/uart8250.hh +++ b/dev/uart8250.hh @@ -82,8 +82,8 @@ class Uart8250 : public Uart Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency, Platform *p); - virtual Fault read(MemReqPtr &req, uint8_t *data); - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); /** -- cgit v1.2.3 From dd11b2c4ffc9121faa7e6976bd211dbb595e9af0 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 17 Feb 2006 15:07:48 -0500 Subject: Get rid of deque (poor memory allocation), switch them over to lists. Beware that using size() on a list is a O(n) operation. dev/ns_gige.hh: Remove typedefs that (I assume) were copied over from etherdev.hh. They were unused in the ns_gige code. --HG-- extra : convert_revision : 577954ec26b899bd6329ce6a4aaa1d9b0ba4f34c --- dev/ns_gige.hh | 3 --- 1 file changed, 3 deletions(-) (limited to 'dev') diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index b65626b7b..181837c8d 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -170,9 +170,6 @@ class NSGigE : public PciDev static const Addr size = sizeof(dp_regs); protected: - typedef std::deque pktbuf_t; - typedef pktbuf_t::iterator pktiter_t; - /** device register file */ dp_regs regs; dp_rom rom; -- cgit v1.2.3 From 463aa6d49d49ba9c383f07207df57bad75c58ec9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 19 Feb 2006 02:34:37 -0500 Subject: Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45 --- dev/alpha_console.cc | 1 + dev/baddev.cc | 1 + dev/ide_ctrl.cc | 1 + dev/ide_disk.cc | 1 + dev/ide_disk.hh | 2 ++ dev/isa_fake.cc | 1 + dev/ns_gige.cc | 1 + dev/pciconfigall.cc | 1 + dev/pcidev.hh | 2 ++ dev/platform.cc | 1 + dev/platform.hh | 2 ++ dev/simple_disk.hh | 22 ++++++++++++---------- dev/sinic.cc | 1 + dev/sinicreg.hh | 4 ++-- dev/tsunami.cc | 2 ++ dev/tsunami.hh | 2 ++ dev/tsunami_cchip.cc | 2 ++ dev/tsunami_io.cc | 2 ++ dev/tsunami_pchip.cc | 2 ++ dev/uart8250.cc | 1 + 20 files changed, 40 insertions(+), 12 deletions(-) (limited to 'dev') diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 38fbbdef0..a7ef8f641 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -53,6 +53,7 @@ #include "sim/system.hh" using namespace std; +using namespace AlphaISA; AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d, System *s, BaseCPU *c, Platform *p, diff --git a/dev/baddev.cc b/dev/baddev.cc index b6ca919e4..62871e348 100644 --- a/dev/baddev.cc +++ b/dev/baddev.cc @@ -46,6 +46,7 @@ #include "sim/system.hh" using namespace std; +using namespace TheISA; BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu, HierParams *hier, Bus *pio_bus, const string &devicename) diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index a5cb0dfd8..18c988b81 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -48,6 +48,7 @@ #include "sim/sim_object.hh" using namespace std; +using namespace TheISA; //// // Initialization and destruction diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc index 9d8bb8825..41400c590 100644 --- a/dev/ide_disk.cc +++ b/dev/ide_disk.cc @@ -53,6 +53,7 @@ #include "arch/isa_traits.hh" using namespace std; +using namespace TheISA; IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys, int id, Tick delay) diff --git a/dev/ide_disk.hh b/dev/ide_disk.hh index a656ca464..32888c81c 100644 --- a/dev/ide_disk.hh +++ b/dev/ide_disk.hh @@ -187,6 +187,8 @@ class IdeController; */ class IdeDisk : public SimObject { + protected: + typedef TheISA::Addr Addr; protected: /** The IDE controller for this disk. */ IdeController *ctrl; diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc index 93c9eedbf..117c9e5ad 100644 --- a/dev/isa_fake.cc +++ b/dev/isa_fake.cc @@ -45,6 +45,7 @@ #include "sim/system.hh" using namespace std; +using namespace TheISA; IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu, HierParams *hier, Bus *pio_bus, Addr size) diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index c28615438..07bf178fc 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -84,6 +84,7 @@ const char *NsDmaState[] = using namespace std; using namespace Net; +using namespace TheISA; /////////////////////////////////////////////////////////////////////// // diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index 1175172c4..c581e1561 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -47,6 +47,7 @@ #include "sim/system.hh" using namespace std; +using namespace TheISA; PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu, diff --git a/dev/pcidev.hh b/dev/pcidev.hh index c8d9685c1..a100bf746 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -53,6 +53,8 @@ class MemoryController; */ class PciConfigData : public SimObject { + protected: + typedef TheISA::Addr Addr; public: /** * Constructor to initialize the devices config space to 0. diff --git a/dev/platform.cc b/dev/platform.cc index 58f94db7b..5b667b12c 100644 --- a/dev/platform.cc +++ b/dev/platform.cc @@ -31,6 +31,7 @@ #include "sim/sim_exit.hh" using namespace std; +using namespace TheISA; Platform::Platform(const string &name, IntrControl *intctrl, PciConfigAll *pci) : SimObject(name), intrctrl(intctrl), pciconfig(pci) diff --git a/dev/platform.hh b/dev/platform.hh index 1ee645454..87810250a 100644 --- a/dev/platform.hh +++ b/dev/platform.hh @@ -44,6 +44,8 @@ class Uart; class Platform : public SimObject { + protected: + typedef TheISA::Addr Addr; public: /** Pointer to the interrupt controller */ IntrControl *intrctrl; diff --git a/dev/simple_disk.hh b/dev/simple_disk.hh index 6560e15c2..f68d5bfff 100644 --- a/dev/simple_disk.hh +++ b/dev/simple_disk.hh @@ -44,19 +44,21 @@ class PhysicalMemory; */ class SimpleDisk : public SimObject { -public: - typedef uint64_t baddr_t; + protected: + typedef TheISA::Addr Addr; + public: + typedef uint64_t baddr_t; -protected: - PhysicalMemory *physmem; - DiskImage *image; + protected: + PhysicalMemory *physmem; + DiskImage *image; -public: - SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img); - ~SimpleDisk(); + public: + SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img); + ~SimpleDisk(); - void read(Addr addr, baddr_t block, int count) const; - void write(Addr addr, baddr_t block, int count); + void read(Addr addr, baddr_t block, int count) const; + void write(Addr addr, baddr_t block, int count); }; #endif // __DEV_SIMPLE_DISK_HH__ diff --git a/dev/sinic.cc b/dev/sinic.cc index e79f80678..829d58d32 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -50,6 +50,7 @@ #include "targetarch/vtophys.hh" using namespace Net; +using namespace TheISA; namespace Sinic { diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh index b7008b4e1..343db6303 100644 --- a/dev/sinicreg.hh +++ b/dev/sinicreg.hh @@ -165,7 +165,7 @@ struct Info /* namespace Regs */ } inline const Regs::Info& -regInfo(Addr daddr) +regInfo(TheISA::Addr daddr) { static Regs::Info invalid = { 0, false, false, false, false, "invalid" }; static Regs::Info info [] = { @@ -201,7 +201,7 @@ regInfo(Addr daddr) } inline bool -regValid(Addr daddr) +regValid(TheISA::Addr daddr) { if (daddr > Regs::Size) return false; diff --git a/dev/tsunami.cc b/dev/tsunami.cc index 760848a00..58fc7434e 100644 --- a/dev/tsunami.cc +++ b/dev/tsunami.cc @@ -46,6 +46,8 @@ #include "sim/system.hh" using namespace std; +//Should this be AlphaISA? +using namespace TheISA; Tsunami::Tsunami(const string &name, System *s, IntrControl *ic, PciConfigAll *pci) diff --git a/dev/tsunami.hh b/dev/tsunami.hh index 7fd91d5b2..79b561ed7 100644 --- a/dev/tsunami.hh +++ b/dev/tsunami.hh @@ -55,6 +55,8 @@ class System; class Tsunami : public Platform { + protected: + typedef TheISA::Addr Addr; public: /** Max number of CPUs in a Tsunami */ static const int Max_CPUs = 64; diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 4cda9ec36..10c08a7a2 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -47,6 +47,8 @@ #include "sim/system.hh" using namespace std; +//Should this be AlphaISA? +using namespace TheISA; TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, MemoryController *mmu, HierParams *hier, diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index 0d0d27570..e90bb5abc 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -50,6 +50,8 @@ #include "mem/functional/memory_control.hh" using namespace std; +//Should this be AlphaISA? +using namespace TheISA; TsunamiIO::RTC::RTC(const string &name, Tsunami* t, Tick i) : _name(name), event(t, i), addr(0) diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index a4c04a79f..706daf9dc 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -47,6 +47,8 @@ #include "sim/system.hh" using namespace std; +//Should this be AlphaISA? +using namespace TheISA; TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, MemoryController *mmu, HierParams *hier, diff --git a/dev/uart8250.cc b/dev/uart8250.cc index a2e782189..99355e28a 100644 --- a/dev/uart8250.cc +++ b/dev/uart8250.cc @@ -46,6 +46,7 @@ #include "sim/builder.hh" using namespace std; +using namespace TheISA; Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit) : Event(&mainEventQueue), uart(u) -- cgit v1.2.3 From 3a0102536bdbf00629e6ba944bd55ee0ec77fb52 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 20 Feb 2006 23:41:50 -0500 Subject: Get rid of the code that delays PIO write accesses until the cache access occurs. The fundamental problem is that a subsequent read that occurs functionally will get a functionally incorrect result that can break driver code. dev/ns_gige.cc: dev/ns_gige.hh: dev/sinic.cc: dev/sinic.hh: get rid of pio_delay write and the associated code to move the write to the cache access function dev/sinicreg.hh: no more write delays python/m5/objects/Ethernet.py: get rid of pio_delay write --HG-- extra : convert_revision : 1dcb51b8f4514e717bc334a782dfdf06d29ae69d --- dev/ns_gige.cc | 61 ++++++++------------------------------------------------- dev/ns_gige.hh | 10 ---------- dev/sinic.cc | 35 +-------------------------------- dev/sinic.hh | 12 ------------ dev/sinicreg.hh | 40 ++++++++++++++++++------------------- 5 files changed, 28 insertions(+), 130 deletions(-) (limited to 'dev') diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 07bf178fc..02eb72ca4 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -131,8 +131,6 @@ NSGigE::NSGigE(Params *p) } else if (p->payload_bus) panic("Must define a header bus if defining a payload bus"); - pioDelayWrite = p->pio_delay_write && pioInterface; - intrDelay = p->intr_delay; dmaReadDelay = p->dma_read_delay; dmaWriteDelay = p->dma_write_delay; @@ -805,13 +803,6 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data) } else if (daddr > 0x3FC) panic("Something is messed up!\n"); - if (pioDelayWrite) { - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; - if (cpu >= writeQueue.size()) - writeQueue.resize(cpu + 1); - writeQueue[cpu].push_back(RegWriteData(daddr, *(uint32_t *)data)); - } - if (req->size == sizeof(uint32_t)) { uint32_t reg = *(uint32_t *)data; uint16_t rfaddr; @@ -824,24 +815,20 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data) if (reg & CR_TXD) { txEnable = false; } else if (reg & CR_TXE) { - if (!pioDelayWrite) { - txEnable = true; + txEnable = true; - // the kernel is enabling the transmit machine - if (txState == txIdle) - txKick(); - } + // the kernel is enabling the transmit machine + if (txState == txIdle) + txKick(); } if (reg & CR_RXD) { rxEnable = false; } else if (reg & CR_RXE) { - if (!pioDelayWrite) { - rxEnable = true; + rxEnable = true; - if (rxState == rxIdle) - rxKick(); - } + if (rxState == rxIdle) + rxKick(); } if (reg & CR_TXR) @@ -2949,38 +2936,9 @@ NSGigE::unserialize(Checkpoint *cp, const std::string §ion) Tick NSGigE::cacheAccess(MemReqPtr &req) { - Addr daddr = req->paddr & 0xfff; DPRINTF(EthernetPIO, "timing access to paddr=%#x (daddr=%#x)\n", - req->paddr, daddr); - - if (!pioDelayWrite || !req->cmd.isWrite()) - return curTick + pioLatency; - - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; - std::list &wq = writeQueue[cpu]; - if (wq.empty()) - panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr); - - const RegWriteData &data = wq.front(); - if (data.daddr != daddr) - panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x", - cpu, data.daddr, daddr); - - if (daddr == CR) { - if ((data.value & (CR_TXD | CR_TXE)) == CR_TXE) { - txEnable = true; - if (txState == txIdle) - txKick(); - } - - if ((data.value & (CR_RXD | CR_RXE)) == CR_RXE) { - rxEnable = true; - if (rxState == rxIdle) - rxKick(); - } - } + req->paddr, req->paddr & 0xfff); - wq.pop_front(); return curTick + pioLatency; } @@ -3040,7 +2998,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) Param dma_write_factor; Param dma_no_allocate; Param pio_latency; - Param pio_delay_write; Param intr_delay; Param rx_delay; @@ -3081,7 +3038,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(dma_write_factor, "multiplier for dma writes"), INIT_PARAM(dma_no_allocate, "Should DMA reads allocate cache lines"), INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"), - INIT_PARAM(pio_delay_write, ""), INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"), INIT_PARAM(rx_delay, "Receive Delay"), @@ -3126,7 +3082,6 @@ CREATE_SIM_OBJECT(NSGigE) params->dma_write_factor = dma_write_factor; params->dma_no_allocate = dma_no_allocate; params->pio_latency = pio_latency; - params->pio_delay_write = pio_delay_write; params->intr_delay = intr_delay; params->rx_delay = rx_delay; diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index 181837c8d..a14fde146 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -236,15 +236,6 @@ class NSGigE : public PciDev uint32_t rxDescCnt; DmaState rxDmaState; - struct RegWriteData { - Addr daddr; - uint32_t value; - RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {} - }; - - std::vector > writeQueue; - bool pioDelayWrite; - bool extstsEnable; /** EEPROM State Machine */ @@ -382,7 +373,6 @@ class NSGigE : public PciDev Tick tx_delay; Tick rx_delay; Tick pio_latency; - bool pio_delay_write; bool dma_desc_free; bool dma_data_free; Tick dma_read_delay; diff --git a/dev/sinic.cc b/dev/sinic.cc index 829d58d32..3f73d81c5 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -113,8 +113,6 @@ Device::Device(Params *p) p->dma_no_allocate); } else if (p->payload_bus) panic("must define a header bus if defining a payload bus"); - - pioDelayWrite = p->pio_delay_write && pioInterface; } Device::~Device() @@ -353,9 +351,6 @@ Device::prepareRead(int cpu, int index) void Device::prepareWrite(int cpu, int index) { - if (cpu >= writeQueue.size()) - writeQueue.resize(cpu + 1); - prepareIO(cpu, index); } @@ -503,11 +498,7 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) prepareWrite(cpu, index); - if (pioDelayWrite) - writeQueue[cpu].push_back(RegWriteData(daddr, reg64)); - - if (!pioDelayWrite || !info.delay_write) - regWrite(daddr, cpu, data); + regWrite(daddr, cpu, data); return NoFault; } @@ -1571,27 +1562,6 @@ Device::cacheAccess(MemReqPtr &req) DPRINTF(EthernetPIO, "timing %s to paddr=%#x bar=%d daddr=%#x\n", req->cmd.toString(), req->paddr, bar, daddr); - if (!pioDelayWrite || !req->cmd.isWrite()) - return curTick + pioLatency; - - if (bar == 0) { - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; - std::list &wq = writeQueue[cpu]; - if (wq.empty()) - panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr); - - const RegWriteData &data = wq.front(); - if (data.daddr != daddr) - panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x", - cpu, data.daddr, daddr); - - const Regs::Info &info = regInfo(data.daddr); - if (info.delay_write) - regWrite(daddr, cpu, (uint8_t *)&data.value); - - wq.pop_front(); - } - return curTick + pioLatency; } @@ -1649,7 +1619,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device) Param dma_write_factor; Param dma_no_allocate; Param pio_latency; - Param pio_delay_write; Param intr_delay; Param rx_delay; @@ -1693,7 +1662,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device) INIT_PARAM(dma_write_factor, "multiplier for dma writes"), INIT_PARAM(dma_no_allocate, "Should we allocat on read in cache"), INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"), - INIT_PARAM(pio_delay_write, ""), INIT_PARAM(intr_delay, "Interrupt Delay"), INIT_PARAM(rx_delay, "Receive Delay"), @@ -1741,7 +1709,6 @@ CREATE_SIM_OBJECT(Device) params->dma_write_factor = dma_write_factor; params->dma_no_allocate = dma_no_allocate; params->pio_latency = pio_latency; - params->pio_delay_write = pio_delay_write; params->intr_delay = intr_delay; params->tx_delay = tx_delay; diff --git a/dev/sinic.hh b/dev/sinic.hh index 7935a7cdc..06751a955 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -283,17 +283,6 @@ class Device : public Base void regWrite(Addr daddr, int cpu, const uint8_t *data); Tick cacheAccess(MemReqPtr &req); - protected: - struct RegWriteData { - Addr daddr; - uint64_t value; - RegWriteData(Addr da, uint64_t val) : daddr(da), value(val) {} - }; - - std::vector > writeQueue; - - bool pioDelayWrite; - /** * Statistics */ @@ -349,7 +338,6 @@ class Device : public Base Bus *header_bus; Bus *payload_bus; Tick pio_latency; - bool pio_delay_write; PhysicalMemory *physmem; IntrControl *intctrl; bool rx_filter; diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh index 343db6303..1378e079d 100644 --- a/dev/sinicreg.hh +++ b/dev/sinicreg.hh @@ -157,8 +157,6 @@ struct Info uint8_t size; bool read; bool write; - bool delay_read; - bool delay_write; const char *name; }; @@ -167,33 +165,33 @@ struct Info inline const Regs::Info& regInfo(TheISA::Addr daddr) { - static Regs::Info invalid = { 0, false, false, false, false, "invalid" }; + static Regs::Info invalid = { 0, false, false, "invalid" }; static Regs::Info info [] = { - { 4, true, true, false, false, "Config" }, - { 4, false, true, false, false, "Command" }, - { 4, true, true, false, false, "IntrStatus" }, - { 4, true, true, false, false, "IntrMask" }, - { 4, true, false, false, false, "RxMaxCopy" }, - { 4, true, false, false, false, "TxMaxCopy" }, - { 4, true, false, false, false, "RxMaxIntr" }, + { 4, true, true, "Config" }, + { 4, false, true, "Command" }, + { 4, true, true, "IntrStatus" }, + { 4, true, true, "IntrMask" }, + { 4, true, false, "RxMaxCopy" }, + { 4, true, false, "TxMaxCopy" }, + { 4, true, false, "RxMaxIntr" }, invalid, - { 4, true, false, false, false, "RxFifoSize" }, - { 4, true, false, false, false, "TxFifoSize" }, - { 4, true, false, false, false, "RxFifoMark" }, - { 4, true, false, false, false, "TxFifoMark" }, - { 8, true, true, false, true, "RxData" }, + { 4, true, false, "RxFifoSize" }, + { 4, true, false, "TxFifoSize" }, + { 4, true, false, "RxFifoMark" }, + { 4, true, false, "TxFifoMark" }, + { 8, true, true, "RxData" }, invalid, - { 8, true, false, false, false, "RxDone" }, + { 8, true, false, "RxDone" }, invalid, - { 8, true, false, false, false, "RxWait" }, + { 8, true, false, "RxWait" }, invalid, - { 8, true, true, false, true, "TxData" }, + { 8, true, true, "TxData" }, invalid, - { 8, true, false, false, false, "TxDone" }, + { 8, true, false, "TxDone" }, invalid, - { 8, true, false, false, false, "TxWait" }, + { 8, true, false, "TxWait" }, invalid, - { 8, true, false, false, false, "HwAddr" }, + { 8, true, false, "HwAddr" }, invalid, }; -- cgit v1.2.3 From c22664845900727493097e961d2bc17fd9c60372 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 20 Feb 2006 23:53:14 -0500 Subject: Finished the implementing the change of the ISA from a class to a namespace dev/sinic.cc: When DPRINTF disappears, reg32 becomes an unused variable. With -Werror, this causes the compile to fail. --HG-- extra : convert_revision : c003c714228491e060155070d192521c53d9e929 --- dev/sinic.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'dev') diff --git a/dev/sinic.cc b/dev/sinic.cc index 829d58d32..6ffd0a664 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -494,11 +494,11 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d", info.name, cpu, daddr, req->paddr, req->vaddr, req->size); - uint32_t reg32 = *(uint32_t *)data; + //uint32_t reg32 = *(uint32_t *)data; uint64_t reg64 = *(uint64_t *)data; DPRINTF(EthernetPIO, "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n", - info.name, cpu, info.size == 4 ? reg32 : reg64, daddr, + info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : reg64, daddr, req->paddr, req->vaddr, req->size); prepareWrite(cpu, index); -- cgit v1.2.3 From 3f7979c99d8dc4f434e3daa2e179616f1669e16e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 21 Feb 2006 03:38:21 -0500 Subject: Made Addr a global type --HG-- extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835 --- dev/ide_disk.hh | 2 -- dev/pcidev.hh | 2 -- dev/platform.hh | 2 -- dev/simple_disk.hh | 2 -- dev/sinicreg.hh | 4 ++-- dev/tsunami.hh | 2 -- 6 files changed, 2 insertions(+), 12 deletions(-) (limited to 'dev') diff --git a/dev/ide_disk.hh b/dev/ide_disk.hh index 32888c81c..a656ca464 100644 --- a/dev/ide_disk.hh +++ b/dev/ide_disk.hh @@ -187,8 +187,6 @@ class IdeController; */ class IdeDisk : public SimObject { - protected: - typedef TheISA::Addr Addr; protected: /** The IDE controller for this disk. */ IdeController *ctrl; diff --git a/dev/pcidev.hh b/dev/pcidev.hh index a100bf746..c8d9685c1 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -53,8 +53,6 @@ class MemoryController; */ class PciConfigData : public SimObject { - protected: - typedef TheISA::Addr Addr; public: /** * Constructor to initialize the devices config space to 0. diff --git a/dev/platform.hh b/dev/platform.hh index 87810250a..1ee645454 100644 --- a/dev/platform.hh +++ b/dev/platform.hh @@ -44,8 +44,6 @@ class Uart; class Platform : public SimObject { - protected: - typedef TheISA::Addr Addr; public: /** Pointer to the interrupt controller */ IntrControl *intrctrl; diff --git a/dev/simple_disk.hh b/dev/simple_disk.hh index f68d5bfff..57f81c5a9 100644 --- a/dev/simple_disk.hh +++ b/dev/simple_disk.hh @@ -44,8 +44,6 @@ class PhysicalMemory; */ class SimpleDisk : public SimObject { - protected: - typedef TheISA::Addr Addr; public: typedef uint64_t baddr_t; diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh index 1378e079d..fc1f4c06b 100644 --- a/dev/sinicreg.hh +++ b/dev/sinicreg.hh @@ -163,7 +163,7 @@ struct Info /* namespace Regs */ } inline const Regs::Info& -regInfo(TheISA::Addr daddr) +regInfo(Addr daddr) { static Regs::Info invalid = { 0, false, false, "invalid" }; static Regs::Info info [] = { @@ -199,7 +199,7 @@ regInfo(TheISA::Addr daddr) } inline bool -regValid(TheISA::Addr daddr) +regValid(Addr daddr) { if (daddr > Regs::Size) return false; diff --git a/dev/tsunami.hh b/dev/tsunami.hh index 79b561ed7..7fd91d5b2 100644 --- a/dev/tsunami.hh +++ b/dev/tsunami.hh @@ -55,8 +55,6 @@ class System; class Tsunami : public Platform { - protected: - typedef TheISA::Addr Addr; public: /** Max number of CPUs in a Tsunami */ static const int Max_CPUs = 64; -- cgit v1.2.3 From 8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 21 Feb 2006 20:10:40 -0500 Subject: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. --HG-- extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb --- dev/alpha_console.cc | 4 ++-- dev/alpha_console.hh | 4 ++-- dev/baddev.cc | 4 ++-- dev/baddev.hh | 4 ++-- dev/ide_ctrl.cc | 4 ++-- dev/ide_ctrl.hh | 4 ++-- dev/isa_fake.cc | 4 ++-- dev/isa_fake.hh | 4 ++-- dev/ns_gige.cc | 4 ++-- dev/ns_gige.hh | 4 ++-- dev/pciconfigall.cc | 4 ++-- dev/pciconfigall.hh | 4 ++-- dev/pcidev.cc | 28 ++++++++++++++-------------- dev/pcidev.hh | 36 ++++++++++++++++++------------------ dev/sinic.cc | 14 +++++++------- dev/sinic.hh | 10 +++++----- dev/tsunami_cchip.cc | 4 ++-- dev/tsunami_cchip.hh | 4 ++-- dev/tsunami_io.cc | 4 ++-- dev/tsunami_io.hh | 4 ++-- dev/tsunami_pchip.cc | 4 ++-- dev/tsunami_pchip.hh | 4 ++-- dev/uart.hh | 4 ++-- dev/uart8250.cc | 4 ++-- dev/uart8250.hh | 4 ++-- 25 files changed, 86 insertions(+), 86 deletions(-) (limited to 'dev') diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index a7ef8f641..0f36e63fb 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -100,7 +100,7 @@ AlphaConsole::startup() alphaAccess->intrClockFrequency = platform->intrFrequency(); } -Fault * +Fault AlphaConsole::read(MemReqPtr &req, uint8_t *data) { memset(data, 0, req->size); @@ -190,7 +190,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault AlphaConsole::write(MemReqPtr &req, const uint8_t *data) { uint64_t val; diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh index 75f0a3a67..74ad795f0 100644 --- a/dev/alpha_console.hh +++ b/dev/alpha_console.hh @@ -110,8 +110,8 @@ class AlphaConsole : public PioDevice /** * memory mapped reads and writes */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * standard serialization routines for checkpointing diff --git a/dev/baddev.cc b/dev/baddev.cc index 62871e348..87d683a5d 100644 --- a/dev/baddev.cc +++ b/dev/baddev.cc @@ -62,7 +62,7 @@ BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu, } -Fault * +Fault BadDevice::read(MemReqPtr &req, uint8_t *data) { @@ -70,7 +70,7 @@ BadDevice::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault BadDevice::write(MemReqPtr &req, const uint8_t *data) { panic("Device %s not imlpmented\n", devname); diff --git a/dev/baddev.hh b/dev/baddev.hh index b7b67e31a..c2a204c05 100644 --- a/dev/baddev.hh +++ b/dev/baddev.hh @@ -71,7 +71,7 @@ class BadDevice : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * On a write event we just panic aand hopefully print a @@ -80,7 +80,7 @@ class BadDevice : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Return how long this access will take. diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index 18c988b81..56682a224 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -391,7 +391,7 @@ IdeController::writeConfig(int offset, int size, const uint8_t *data) } } -Fault * +Fault IdeController::read(MemReqPtr &req, uint8_t *data) { Addr offset; @@ -461,7 +461,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault IdeController::write(MemReqPtr &req, const uint8_t *data) { Addr offset; diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh index 72523f57c..0fbaf9207 100644 --- a/dev/ide_ctrl.hh +++ b/dev/ide_ctrl.hh @@ -213,7 +213,7 @@ class IdeController : public PciDev * @param data Return the field read. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * Write to the mmapped I/O control registers. @@ -221,7 +221,7 @@ class IdeController : public PciDev * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Serialize this object to the given output stream. diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc index 117c9e5ad..2afebbded 100644 --- a/dev/isa_fake.cc +++ b/dev/isa_fake.cc @@ -60,7 +60,7 @@ IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu, } } -Fault * +Fault IsaFake::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "read va=%#x size=%d\n", @@ -93,7 +93,7 @@ IsaFake::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault IsaFake::write(MemReqPtr &req, const uint8_t *data) { DPRINTF(Tsunami, "write - va=%#x size=%d \n", diff --git a/dev/isa_fake.hh b/dev/isa_fake.hh index 60ca5f90a..290b24b54 100644 --- a/dev/isa_fake.hh +++ b/dev/isa_fake.hh @@ -65,14 +65,14 @@ class IsaFake : public PioDevice * @param req The memory request. * @param data Where to put the data. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * All writes are simply ignored. * @param req The memory request. * @param data the data to not write. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Return how long this access will take. diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 02eb72ca4..4b08d8497 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -557,7 +557,7 @@ NSGigE::writeConfig(int offset, int size, const uint8_t* data) * This reads the device registers, which are detailed in the NS83820 * spec sheet */ -Fault * +Fault NSGigE::read(MemReqPtr &req, uint8_t *data) { assert(ioEnable); @@ -786,7 +786,7 @@ NSGigE::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault NSGigE::write(MemReqPtr &req, const uint8_t *data) { assert(ioEnable); diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index a14fde146..cdd8e4b9e 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -395,8 +395,8 @@ class NSGigE : public PciDev virtual void writeConfig(int offset, int size, const uint8_t *data); virtual void readConfig(int offset, int size, uint8_t *data); - virtual Fault * read(MemReqPtr &req, uint8_t *data); - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); bool cpuIntrPending() const; void cpuIntrAck() { cpuIntrClear(); } diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index c581e1561..d55084fa5 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -96,7 +96,7 @@ PciConfigAll::startup() } -Fault * +Fault PciConfigAll::read(MemReqPtr &req, uint8_t *data) { @@ -144,7 +144,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault PciConfigAll::write(MemReqPtr &req, const uint8_t *data) { Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); diff --git a/dev/pciconfigall.hh b/dev/pciconfigall.hh index 6df033286..c6a0241d8 100644 --- a/dev/pciconfigall.hh +++ b/dev/pciconfigall.hh @@ -103,7 +103,7 @@ class PciConfigAll : public PioDevice * @param data Return the field read. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * Write to PCI config spcae. If the device does not exit the simulator @@ -114,7 +114,7 @@ class PciConfigAll : public PioDevice * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Start up function to check if more than one person is using an interrupt line diff --git a/dev/pcidev.cc b/dev/pcidev.cc index c469e716a..a05ee3803 100644 --- a/dev/pcidev.cc +++ b/dev/pcidev.cc @@ -70,59 +70,59 @@ PciDev::PciDev(Params *p) p->configSpace->registerDevice(p->deviceNum, p->functionNum, this); } -Fault * +Fault PciDev::read(MemReqPtr &req, uint8_t *data) { return NoFault; } -Fault * +Fault PciDev::write(MemReqPtr &req, const uint8_t *data) { return NoFault; } -Fault * +Fault PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } -Fault * +Fault PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data) { panic("not implemented"); } diff --git a/dev/pcidev.hh b/dev/pcidev.hh index c8d9685c1..9427463bf 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -189,37 +189,37 @@ class PciDev : public DmaDevice */ PciDev(Params *params); - virtual Fault * read(MemReqPtr &req, uint8_t *data); - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); public: /** * Implement the read/write as BAR accesses */ - Fault * readBar(MemReqPtr &req, uint8_t *data); - Fault * writeBar(MemReqPtr &req, const uint8_t *data); + Fault readBar(MemReqPtr &req, uint8_t *data); + Fault writeBar(MemReqPtr &req, const uint8_t *data); public: /** * Read from a specific BAR */ - virtual Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault * readBar1(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault * readBar2(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault * readBar3(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault * readBar4(MemReqPtr &req, Addr daddr, uint8_t *data); - virtual Fault * readBar5(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar1(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar2(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar3(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar4(MemReqPtr &req, Addr daddr, uint8_t *data); + virtual Fault readBar5(MemReqPtr &req, Addr daddr, uint8_t *data); public: /** * Write to a specific BAR */ - virtual Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault * writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault * writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault * writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault * writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data); - virtual Fault * writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data); + virtual Fault writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data); public: /** @@ -257,7 +257,7 @@ class PciDev : public DmaDevice virtual void unserialize(Checkpoint *cp, const std::string §ion); }; -inline Fault * +inline Fault PciDev::readBar(MemReqPtr &req, uint8_t *data) { if (isBAR(req->paddr, 0)) @@ -275,7 +275,7 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data) return MachineCheckFault; } -inline Fault * +inline Fault PciDev::writeBar(MemReqPtr &req, const uint8_t *data) { if (isBAR(req->paddr, 0)) diff --git a/dev/sinic.cc b/dev/sinic.cc index d175a1796..c499d2f49 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -357,11 +357,11 @@ Device::prepareWrite(int cpu, int index) /** * I/O read of device register */ -Fault * +Fault Device::read(MemReqPtr &req, uint8_t *data) { assert(config.command & PCI_CMD_MSE); - Fault * fault = readBar(req, data); + Fault fault = readBar(req, data); if (fault == MachineCheckFault) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", @@ -373,7 +373,7 @@ Device::read(MemReqPtr &req, uint8_t *data) return fault; } -Fault * +Fault Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) { int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; @@ -423,7 +423,7 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) /** * IPR read of device register */ -Fault * +Fault Device::iprRead(Addr daddr, int cpu, uint64_t &result) { if (!regValid(daddr)) @@ -453,11 +453,11 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result) /** * I/O write of device register */ -Fault * +Fault Device::write(MemReqPtr &req, const uint8_t *data) { assert(config.command & PCI_CMD_MSE); - Fault * fault = writeBar(req, data); + Fault fault = writeBar(req, data); if (fault == MachineCheckFault) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", @@ -469,7 +469,7 @@ Device::write(MemReqPtr &req, const uint8_t *data) return fault; } -Fault * +Fault Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) { int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; diff --git a/dev/sinic.hh b/dev/sinic.hh index 06751a955..97ebf4c30 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -271,15 +271,15 @@ class Device : public Base * Memory Interface */ public: - virtual Fault * read(MemReqPtr &req, uint8_t *data); - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); void prepareIO(int cpu, int index); void prepareRead(int cpu, int index); void prepareWrite(int cpu, int index); - Fault * iprRead(Addr daddr, int cpu, uint64_t &result); - Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); - Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); + Fault iprRead(Addr daddr, int cpu, uint64_t &result); + Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); + Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); void regWrite(Addr daddr, int cpu, const uint8_t *data); Tick cacheAccess(MemReqPtr &req); diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 10c08a7a2..4dc4413a1 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -78,7 +78,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, tsunami->cchip = this; } -Fault * +Fault TsunamiCChip::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size); @@ -192,7 +192,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) { DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n", diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh index dadbdb0e3..d88ad375f 100644 --- a/dev/tsunami_cchip.hh +++ b/dev/tsunami_cchip.hh @@ -105,7 +105,7 @@ class TsunamiCChip : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** @@ -114,7 +114,7 @@ class TsunamiCChip : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * post an RTC interrupt to the CPU diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index e90bb5abc..e66d6653b 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -446,7 +446,7 @@ TsunamiIO::frequency() const return Clock::Frequency / clockInterval; } -Fault * +Fault TsunamiIO::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", @@ -523,7 +523,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault TsunamiIO::write(MemReqPtr &req, const uint8_t *data) { diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh index 3b26ebfaa..b024ecd14 100644 --- a/dev/tsunami_io.hh +++ b/dev/tsunami_io.hh @@ -330,7 +330,7 @@ class TsunamiIO : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * Process a write to one of the devices we emulate. @@ -338,7 +338,7 @@ class TsunamiIO : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Post an PIC interrupt to the CPU via the CChip diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index 706daf9dc..46efc3dfe 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -78,7 +78,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, tsunami->pchip = this; } -Fault * +Fault TsunamiPChip::read(MemReqPtr &req, uint8_t *data) { DPRINTF(Tsunami, "read va=%#x size=%d\n", @@ -167,7 +167,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data) return NoFault; } -Fault * +Fault TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) { DPRINTF(Tsunami, "write - va=%#x size=%d \n", diff --git a/dev/tsunami_pchip.hh b/dev/tsunami_pchip.hh index ff888bea1..c1d95431b 100644 --- a/dev/tsunami_pchip.hh +++ b/dev/tsunami_pchip.hh @@ -99,7 +99,7 @@ class TsunamiPChip : public PioDevice * @param data A pointer to write the read data to. * @return The fault condition of the access. */ - virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); /** * Process a write to the PChip. @@ -107,7 +107,7 @@ class TsunamiPChip : public PioDevice * @param data The data to write. * @return The fault condition of the access. */ - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * Serialize this object to the given output stream. diff --git a/dev/uart.hh b/dev/uart.hh index 96c22025c..145b9ca9e 100644 --- a/dev/uart.hh +++ b/dev/uart.hh @@ -57,8 +57,8 @@ class Uart : public PioDevice Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p); - virtual Fault * read(MemReqPtr &req, uint8_t *data) = 0; - virtual Fault * write(MemReqPtr &req, const uint8_t *data) = 0; + virtual Fault read(MemReqPtr &req, uint8_t *data) = 0; + virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0; /** diff --git a/dev/uart8250.cc b/dev/uart8250.cc index 99355e28a..65bccee86 100644 --- a/dev/uart8250.cc +++ b/dev/uart8250.cc @@ -112,7 +112,7 @@ Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu, } -Fault * +Fault Uart8250::read(MemReqPtr &req, uint8_t *data) { Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); @@ -188,7 +188,7 @@ Uart8250::read(MemReqPtr &req, uint8_t *data) } -Fault * +Fault Uart8250::write(MemReqPtr &req, const uint8_t *data) { Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); diff --git a/dev/uart8250.hh b/dev/uart8250.hh index a0e2d344a..88abf8e24 100644 --- a/dev/uart8250.hh +++ b/dev/uart8250.hh @@ -82,8 +82,8 @@ class Uart8250 : public Uart Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency, Platform *p); - virtual Fault * read(MemReqPtr &req, uint8_t *data); - virtual Fault * write(MemReqPtr &req, const uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** -- cgit v1.2.3 From 1166d4f0bfe67a9dc178be3454b4f0eac38663ad Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 23 Feb 2006 14:50:16 -0500 Subject: Get rid of the xc from the alphaAccess/alphaConsole backdoor device. Now allocate an array of stacks indexed by cpu number which specify cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for their stacks before continuing. This change *REQUIRES* a the new console code to operate correctly. arch/alpha/ev5.cc: Add cpuId to initCPU/initIPR functions cpu/o3/cpu.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Move the cpu initilization into an init() function since it now needs the CPU id which isn't known at construction dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: instead of the bootstrap variables, add space for 64 cpu stacks in the alpha access structure. sim/system.cc: start all cpus immediately rather than just the first one --HG-- extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b --- dev/alpha_access.h | 6 ++---- dev/alpha_console.cc | 46 ++++++++++++++++++---------------------------- dev/alpha_console.hh | 2 +- 3 files changed, 21 insertions(+), 33 deletions(-) (limited to 'dev') diff --git a/dev/alpha_access.h b/dev/alpha_access.h index a20a05535..5a1df6f39 100644 --- a/dev/alpha_access.h +++ b/dev/alpha_access.h @@ -33,7 +33,7 @@ * System Console Memory Mapped Register Definition */ -#define ALPHA_ACCESS_VERSION (1303) +#define ALPHA_ACCESS_VERSION (1305) #ifdef CONSOLE typedef unsigned uint32_t; @@ -67,9 +67,7 @@ struct AlphaAccess uint64_t inputChar; // 68: Placeholder for input // MP boot - uint64_t bootStrapImpure; // 70: - uint32_t bootStrapCPU; // 78: - uint32_t align2; // 7C: Dummy placeholder for alignment + uint64_t cpuStack[64]; // 70: }; #endif // __ALPHA_ACCESS_H__ diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 61b444628..a520e7ea9 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -80,9 +80,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d, alphaAccess->diskOperation = 0; alphaAccess->outputChar = 0; alphaAccess->inputChar = 0; - alphaAccess->bootStrapImpure = 0; - alphaAccess->bootStrapCPU = 0; - alphaAccess->align2 = 0; + bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack)); system->setAlphaAccess(addr); } @@ -122,9 +120,6 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) case offsetof(AlphaAccess, numCPUs): *(uint32_t*)data = alphaAccess->numCPUs; break; - case offsetof(AlphaAccess, bootStrapCPU): - *(uint32_t*)data = alphaAccess->bootStrapCPU; - break; case offsetof(AlphaAccess, intrClockFrequency): *(uint32_t*)data = alphaAccess->intrClockFrequency; break; @@ -175,11 +170,14 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) case offsetof(AlphaAccess, outputChar): *(uint64_t*)data = alphaAccess->outputChar; break; - case offsetof(AlphaAccess, bootStrapImpure): - *(uint64_t*)data = alphaAccess->bootStrapImpure; - break; default: - panic("Unknown 64bit access, %#x\n", daddr); + int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / + sizeof(alphaAccess->cpuStack[0]); + + if (cpunum >= 0 && cpunum < 64) + *(uint64_t*)data = alphaAccess->cpuStack[cpunum]; + else + panic("Unknown 64bit access, %#x\n", daddr); } break; default: @@ -239,24 +237,18 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) console->out((char)(val & 0xff)); break; - case offsetof(AlphaAccess, bootStrapImpure): - alphaAccess->bootStrapImpure = val; - break; - - case offsetof(AlphaAccess, bootStrapCPU): - warn("%d: Trying to launch another CPU!", curTick); - assert(val > 0 && "Must not access primary cpu"); - - other_xc = req->xc->system->execContexts[val]; - other_xc->regs.intRegFile[16] = val; - other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val; - other_xc->regs.intRegFile[0] = val; - other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure; other_xc->activate(); //Start the cpu break; default: - return Machine_Check_Fault; + int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / + sizeof(alphaAccess->cpuStack[0]); + warn("%d: Trying to launch CPU number %d!", curTick, cpunum); + assert(val > 0 && "Must not access primary cpu"); + if (cpunum >= 0 && cpunum < 64) + alphaAccess->cpuStack[cpunum] = val; + else + panic("Unknown 64bit access, %#x\n", daddr); } return No_Fault; @@ -287,8 +279,7 @@ AlphaConsole::Access::serialize(ostream &os) SERIALIZE_SCALAR(diskOperation); SERIALIZE_SCALAR(outputChar); SERIALIZE_SCALAR(inputChar); - SERIALIZE_SCALAR(bootStrapImpure); - SERIALIZE_SCALAR(bootStrapCPU); + SERIALIZE_ARRAY(cpuStack,64); } void @@ -310,8 +301,7 @@ AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_SCALAR(diskOperation); UNSERIALIZE_SCALAR(outputChar); UNSERIALIZE_SCALAR(inputChar); - UNSERIALIZE_SCALAR(bootStrapImpure); - UNSERIALIZE_SCALAR(bootStrapCPU); + UNSERIALIZE_ARRAY(cpuStack, 64); } void diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh index 74ad795f0..2d1c1e634 100644 --- a/dev/alpha_console.hh +++ b/dev/alpha_console.hh @@ -96,7 +96,7 @@ class AlphaConsole : public PioDevice BaseCPU *cpu; Addr addr; - static const Addr size = 0x80; // equal to sizeof(alpha_access); + static const Addr size = sizeof(struct AlphaAccess); public: /** Standard Constructor */ -- cgit v1.2.3 From 08637efadc40a1003d68bba91dedb007fe10798c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 24 Feb 2006 01:51:45 -0500 Subject: Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type. arch/alpha/alpha_memory.cc: arch/alpha/isa/decoder.isa: Added news where faults are created. arch/alpha/ev5.cc: Changed places where a fault was compared to a fault type to use isA rather than == arch/alpha/faults.cc: arch/alpha/faults.hh: Changed Fault to be a RefCountingPtr arch/alpha/isa/fp.isa: Added a new where a FloatEnableFault was created. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: Added a new where an UnimplementedFault is created. base/refcnt.hh: Added include of stddef.h for the NULL macro cpu/base_dyn_inst.cc: Added a new where an UnimplementedOpcodeFault is created. cpu/o3/alpha_cpu_impl.hh: Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name() cpu/o3/regfile.hh: Added new where UnimplementedOpcodeFaults are created. cpu/simple/cpu.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created. dev/alpha_console.cc: Added news where MachineCheckFaults are created. dev/pcidev.hh: Added news where MachineCheckFaults are generated. dev/sinic.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables. kern/kernel_stats.cc: Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future. kern/kernel_stats.hh: Commented out the declaration of _fault. when fault() is called, the fault increments its own stat. sim/faults.cc: sim/faults.hh: Changed Fault from a FaultBase * to a RefCountingPtr. --HG-- extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d --- dev/alpha_console.cc | 6 +++--- dev/pcidev.hh | 4 ++-- dev/sinic.cc | 19 ++++++++++++------- 3 files changed, 17 insertions(+), 12 deletions(-) (limited to 'dev') diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 0f36e63fb..87d8c4e93 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -184,7 +184,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) } break; default: - return MachineCheckFault; + return new MachineCheckFault; } return NoFault; @@ -204,7 +204,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) val = *(uint64_t *)data; break; default: - return MachineCheckFault; + return new MachineCheckFault; } Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); @@ -257,7 +257,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) break; default: - return MachineCheckFault; + return new MachineCheckFault; } return NoFault; diff --git a/dev/pcidev.hh b/dev/pcidev.hh index 9427463bf..4f08c2cf9 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -272,7 +272,7 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data) return readBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return readBar5(req, req->paddr - BARAddrs[5], data); - return MachineCheckFault; + return new MachineCheckFault; } inline Fault @@ -290,7 +290,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data) return writeBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return writeBar5(req, req->paddr - BARAddrs[5], data); - return MachineCheckFault; + return new MachineCheckFault; } #endif // __DEV_PCIDEV_HH__ diff --git a/dev/sinic.cc b/dev/sinic.cc index c499d2f49..3f7226817 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -363,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data) assert(config.command & PCI_CMD_MSE); Fault fault = readBar(req, data); - if (fault == MachineCheckFault) { + if (fault->isA()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return MachineCheckFault; + return new MachineCheckFault; } return fault; @@ -459,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data) assert(config.command & PCI_CMD_MSE); Fault fault = writeBar(req, data); - if (fault == MachineCheckFault) { + if (fault->isA()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return MachineCheckFault; + return new MachineCheckFault; } return fault; @@ -489,12 +489,17 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d", info.name, cpu, daddr, req->paddr, req->vaddr, req->size); + //These are commmented out because when the DPRINTF below isn't used, + //these values aren't used and gcc issues a warning. With -Werror, + //this prevents compilation. //uint32_t reg32 = *(uint32_t *)data; - uint64_t reg64 = *(uint64_t *)data; + //uint64_t reg64 = *(uint64_t *)data; DPRINTF(EthernetPIO, "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n", - info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : reg64, daddr, - req->paddr, req->vaddr, req->size); + info.name, cpu, info.size == 4 ? + (*(uint32_t *)data) : + (*(uint32_t *)data), + daddr, req->paddr, req->vaddr, req->size); prepareWrite(cpu, index); -- cgit v1.2.3 From 25b39da69d4267b34a87b7324008b6d4480a2b09 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 25 Feb 2006 22:01:05 -0500 Subject: Since the delayed write stuff is gone, get rid of regWrite and merge it with writeBar0 --HG-- extra : convert_revision : 354642e0d528b6a5a7f2cdf0264d93e738b2d4eb --- dev/sinic.cc | 23 ++++++----------------- dev/sinic.hh | 1 - 2 files changed, 6 insertions(+), 18 deletions(-) (limited to 'dev') diff --git a/dev/sinic.cc b/dev/sinic.cc index c499d2f49..a9363954b 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -489,30 +489,17 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d", info.name, cpu, daddr, req->paddr, req->vaddr, req->size); - //uint32_t reg32 = *(uint32_t *)data; + uint32_t reg32 = *(uint32_t *)data; uint64_t reg64 = *(uint64_t *)data; + VirtualReg &vnic = virtualRegs[index]; + DPRINTF(EthernetPIO, "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n", - info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : reg64, daddr, + info.name, cpu, info.size == 4 ? reg32 : reg64, daddr, req->paddr, req->vaddr, req->size); prepareWrite(cpu, index); - regWrite(daddr, cpu, data); - - return NoFault; -} - -void -Device::regWrite(Addr daddr, int cpu, const uint8_t *data) -{ - Addr index = daddr >> Regs::VirtualShift; - Addr raddr = daddr & Regs::VirtualMask; - - uint32_t reg32 = *(uint32_t *)data; - uint64_t reg64 = *(uint64_t *)data; - VirtualReg &vnic = virtualRegs[index]; - switch (raddr) { case Regs::Config: changeConfig(reg32); @@ -559,6 +546,8 @@ Device::regWrite(Addr daddr, int cpu, const uint8_t *data) } break; } + + return NoFault; } void diff --git a/dev/sinic.hh b/dev/sinic.hh index 97ebf4c30..c4027be86 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -280,7 +280,6 @@ class Device : public Base Fault iprRead(Addr daddr, int cpu, uint64_t &result); Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); - void regWrite(Addr daddr, int cpu, const uint8_t *data); Tick cacheAccess(MemReqPtr &req); /** -- cgit v1.2.3 From 9b18c0e87272b35a34e39ce2a9924963402e5b29 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 26 Feb 2006 20:31:08 -0500 Subject: add some support for random access of data in packet fifos dev/pktfifo.cc: add support for copying arbitrary data out of a packet fifo dev/pktfifo.hh: add support for copying arbitrary data out of a packet fifo. Add functions to determine where in the fifo a particular packet is --HG-- extra : convert_revision : f8ddc994ce8577f29af0de3fa418a01e4e2cb0f1 --- dev/pktfifo.cc | 34 ++++++++++++++++++++++++++++++++-- dev/pktfifo.hh | 29 +++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 2 deletions(-) (limited to 'dev') diff --git a/dev/pktfifo.cc b/dev/pktfifo.cc index b4fab2d6f..639009be9 100644 --- a/dev/pktfifo.cc +++ b/dev/pktfifo.cc @@ -31,6 +31,36 @@ using namespace std; +bool +PacketFifo::copyout(void *dest, int offset, int len) +{ + char *data = (char *)dest; + if (offset + len >= size()) + return false; + + list::iterator p = fifo.begin(); + list::iterator end = fifo.end(); + while (len > 0) { + while (offset >= (*p)->length) { + offset -= (*p)->length; + ++p; + } + + if (p == end) + panic("invalid fifo"); + + int size = min((*p)->length - offset, len); + memcpy(data, (*p)->data, size); + offset = 0; + len -= size; + data += size; + ++p; + } + + return true; +} + + void PacketFifo::serialize(const string &base, ostream &os) { @@ -40,8 +70,8 @@ PacketFifo::serialize(const string &base, ostream &os) paramOut(os, base + ".packets", fifo.size()); int i = 0; - std::list::iterator p = fifo.begin(); - std::list::iterator end = fifo.end(); + list::iterator p = fifo.begin(); + list::iterator end = fifo.end(); while (p != end) { (*p)->serialize(csprintf("%s.packet%d", base, i), os); ++p; diff --git a/dev/pktfifo.hh b/dev/pktfifo.hh index e63fd291f..e245840a8 100644 --- a/dev/pktfifo.hh +++ b/dev/pktfifo.hh @@ -127,6 +127,35 @@ class PacketFifo fifo.erase(i); } + bool copyout(void *dest, int offset, int len); + + int countPacketsBefore(iterator end) + { + iterator i = fifo.begin(); + int count = 0; + + while (i != end) { + ++count; + ++i; + } + + return count; + } + + int countPacketsAfter(iterator i) + { + iterator end = fifo.end(); + int count = 0; + + while (i != end) { + ++count; + ++i; + } + + return count; + } + + /** * Serialization stuff */ -- cgit v1.2.3 From 444f520f7e2da9468fa622dcf51859915bd31fd6 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 03:57:15 -0500 Subject: MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. arch/alpha/alpha_memory.cc: cpu/base_dyn_inst.cc: dev/alpha_console.cc: dev/pcidev.hh: dev/sinic.cc: MachineCheckFaults are now generated by the ISA, rather than being created directly. --HG-- extra : convert_revision : 34a7da41639e93be21ed70dac681b27480008d19 --- dev/alpha_console.cc | 4 ++-- dev/pcidev.hh | 6 ++++-- dev/sinic.cc | 8 ++++---- 3 files changed, 10 insertions(+), 8 deletions(-) (limited to 'dev') diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 85134b435..c8327736f 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -182,7 +182,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) } break; default: - return new MachineCheckFault; + return genMachineCheckFault(); } return NoFault; @@ -202,7 +202,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) val = *(uint64_t *)data; break; default: - return new MachineCheckFault; + return genMachineCheckFault(); } Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); diff --git a/dev/pcidev.hh b/dev/pcidev.hh index 4f08c2cf9..bdfc6b932 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -260,6 +260,7 @@ class PciDev : public DmaDevice inline Fault PciDev::readBar(MemReqPtr &req, uint8_t *data) { + using namespace TheISA; if (isBAR(req->paddr, 0)) return readBar0(req, req->paddr - BARAddrs[0], data); if (isBAR(req->paddr, 1)) @@ -272,12 +273,13 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data) return readBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return readBar5(req, req->paddr - BARAddrs[5], data); - return new MachineCheckFault; + return genMachineCheckFault(); } inline Fault PciDev::writeBar(MemReqPtr &req, const uint8_t *data) { + using namespace TheISA; if (isBAR(req->paddr, 0)) return writeBar0(req, req->paddr - BARAddrs[0], data); if (isBAR(req->paddr, 1)) @@ -290,7 +292,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data) return writeBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return writeBar5(req, req->paddr - BARAddrs[5], data); - return new MachineCheckFault; + return genMachineCheckFault(); } #endif // __DEV_PCIDEV_HH__ diff --git a/dev/sinic.cc b/dev/sinic.cc index 3f7226817..ba643de4b 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -363,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data) assert(config.command & PCI_CMD_MSE); Fault fault = readBar(req, data); - if (fault->isA()) { + if (fault->isMachineCheckFault()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return new MachineCheckFault; + return genMachineCheckFault(); } return fault; @@ -459,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data) assert(config.command & PCI_CMD_MSE); Fault fault = writeBar(req, data); - if (fault->isA()) { + if (fault->isMachineCheckFault()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return new MachineCheckFault; + return genMachineCheckFault(); } return fault; -- cgit v1.2.3 From c5dcd152f264a837f50d39f98d0f4f81478e3553 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 05:35:43 -0500 Subject: Changed targetarch to just arch. SConscript: Changed all of the "targetarch" files to be "arch" files arch/SConscript: Added all of the remaining targetarch files to isa_switch_hdrs --HG-- extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480 --- dev/ns_gige.cc | 2 +- dev/sinic.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'dev') diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 4b08d8497..d6df347bc 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -49,7 +49,7 @@ #include "sim/debug.hh" #include "sim/host.hh" #include "sim/stats.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" const char *NsRxStateStrings[] = { diff --git a/dev/sinic.cc b/dev/sinic.cc index ba643de4b..c28ab335b 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -47,7 +47,7 @@ #include "sim/eventq.hh" #include "sim/host.hh" #include "sim/stats.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace Net; using namespace TheISA; -- cgit v1.2.3 From 70b35bab5778799805fe9b6040b23eb1885dbfc3 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 27 Feb 2006 11:44:35 -0500 Subject: Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs. They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76 --- dev/sinic.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'dev') diff --git a/dev/sinic.cc b/dev/sinic.cc index c499d2f49..84f5c70df 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -376,7 +376,7 @@ Device::read(MemReqPtr &req, uint8_t *data) Fault Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) { - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; + int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; @@ -472,7 +472,7 @@ Device::write(MemReqPtr &req, const uint8_t *data) Fault Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) { - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; + int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; -- cgit v1.2.3 From 8e6b8cb212ba79978056b57dd60c60a39f6428e9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 28 Feb 2006 06:17:57 -0500 Subject: Hand merged --HG-- extra : convert_revision : 0fd5ecbba5dc6299dd046926ec27595ca4d97ee7 --- dev/sinic.cc | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) (limited to 'dev') diff --git a/dev/sinic.cc b/dev/sinic.cc index c28ab335b..1c0e59e0a 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -494,30 +494,17 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) //this prevents compilation. //uint32_t reg32 = *(uint32_t *)data; //uint64_t reg64 = *(uint64_t *)data; + VirtualReg &vnic = virtualRegs[index]; + DPRINTF(EthernetPIO, "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n", info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : - (*(uint32_t *)data), + (*(uint64_t *)data), daddr, req->paddr, req->vaddr, req->size); prepareWrite(cpu, index); - regWrite(daddr, cpu, data); - - return NoFault; -} - -void -Device::regWrite(Addr daddr, int cpu, const uint8_t *data) -{ - Addr index = daddr >> Regs::VirtualShift; - Addr raddr = daddr & Regs::VirtualMask; - - uint32_t reg32 = *(uint32_t *)data; - uint64_t reg64 = *(uint64_t *)data; - VirtualReg &vnic = virtualRegs[index]; - switch (raddr) { case Regs::Config: changeConfig(reg32); @@ -564,6 +551,8 @@ Device::regWrite(Addr daddr, int cpu, const uint8_t *data) } break; } + + return NoFault; } void -- cgit v1.2.3 From 3a362d04b7aed0fa728af9373bad175a096a7de8 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 28 Feb 2006 06:28:09 -0500 Subject: Corrected some mistakes in the hand merge --HG-- extra : convert_revision : 84d852e625f754c4414403e8c3e26bda80500d4f --- dev/sinic.cc | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'dev') diff --git a/dev/sinic.cc b/dev/sinic.cc index 1c0e59e0a..31d651249 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -489,18 +489,13 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d", info.name, cpu, daddr, req->paddr, req->vaddr, req->size); - //These are commmented out because when the DPRINTF below isn't used, - //these values aren't used and gcc issues a warning. With -Werror, - //this prevents compilation. - //uint32_t reg32 = *(uint32_t *)data; - //uint64_t reg64 = *(uint64_t *)data; + uint32_t reg32 = *(uint32_t *)data; + uint64_t reg64 = *(uint64_t *)data; VirtualReg &vnic = virtualRegs[index]; DPRINTF(EthernetPIO, "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n", - info.name, cpu, info.size == 4 ? - (*(uint32_t *)data) : - (*(uint64_t *)data), + info.name, cpu, info.size == 4 ? reg32 : reg64, daddr, req->paddr, req->vaddr, req->size); prepareWrite(cpu, index); -- cgit v1.2.3 From 7546fabe68a1dc6ec9b9e020f5e2b1cc0aa31c21 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 3 Mar 2006 14:17:48 -0500 Subject: Ethernet devices have an RSS option to tell the driver to use Receive side scaling dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: add support for setting the RSS flag to notify the driver to use RSS --HG-- extra : convert_revision : 5f0c11668ae976634b3bf0caad669a9464a4c041 --- dev/ns_gige.cc | 7 ++++++- dev/ns_gige.hh | 1 + dev/ns_gige_reg.h | 1 + dev/sinic.cc | 7 ++++++- dev/sinic.hh | 1 + dev/sinicreg.hh | 1 + 6 files changed, 16 insertions(+), 2 deletions(-) (limited to 'dev') diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index d6df347bc..ed8c794f9 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -767,6 +767,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data) reg |= M5REG_RX_THREAD; if (params()->tx_thread) reg |= M5REG_TX_THREAD; + if (params()->rss) + reg |= M5REG_RSS; break; default: @@ -3009,6 +3011,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) Param hardware_address; Param rx_thread; Param tx_thread; + Param rss; END_DECLARE_SIM_OBJECT_PARAMS(NSGigE) @@ -3048,7 +3051,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(rx_filter, "Enable Receive Filter"), INIT_PARAM(hardware_address, "Ethernet Hardware Address"), INIT_PARAM(rx_thread, ""), - INIT_PARAM(tx_thread, "") + INIT_PARAM(tx_thread, ""), + INIT_PARAM(rss, "") END_INIT_SIM_OBJECT_PARAMS(NSGigE) @@ -3093,6 +3097,7 @@ CREATE_SIM_OBJECT(NSGigE) params->eaddr = hardware_address; params->rx_thread = rx_thread; params->tx_thread = tx_thread; + params->rss = rss; return new NSGigE(params); } diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index cdd8e4b9e..59c55056e 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -385,6 +385,7 @@ class NSGigE : public PciDev uint32_t rx_fifo_size; bool rx_thread; bool tx_thread; + bool rss; bool dma_no_allocate; }; diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h index eadc60d03..5f6fa2cc5 100644 --- a/dev/ns_gige_reg.h +++ b/dev/ns_gige_reg.h @@ -306,6 +306,7 @@ /* M5 control register */ #define M5REG_RESERVED 0xfffffffc +#define M5REG_RSS 0x00000004 #define M5REG_RX_THREAD 0x00000002 #define M5REG_TX_THREAD 0x00000001 diff --git a/dev/sinic.cc b/dev/sinic.cc index 34b4213e0..363994919 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -761,6 +761,8 @@ Device::reset() regs.Config |= Config_RxThread; if (params()->tx_thread) regs.Config |= Config_TxThread; + if (params()->rss) + regs.Config |= Config_RSS; regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow; regs.RxMaxCopy = params()->rx_max_copy; regs.TxMaxCopy = params()->tx_max_copy; @@ -1624,6 +1626,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device) Param hardware_address; Param rx_thread; Param tx_thread; + Param rss; END_DECLARE_SIM_OBJECT_PARAMS(Device) @@ -1666,7 +1669,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device) INIT_PARAM(rx_filter, "Enable Receive Filter"), INIT_PARAM(hardware_address, "Ethernet Hardware Address"), INIT_PARAM(rx_thread, ""), - INIT_PARAM(tx_thread, "") + INIT_PARAM(tx_thread, ""), + INIT_PARAM(rss, "") END_INIT_SIM_OBJECT_PARAMS(Device) @@ -1714,6 +1718,7 @@ CREATE_SIM_OBJECT(Device) params->eaddr = hardware_address; params->rx_thread = rx_thread; params->tx_thread = tx_thread; + params->rss = rss; return new Device(params); } diff --git a/dev/sinic.hh b/dev/sinic.hh index c4027be86..25172fa45 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -355,6 +355,7 @@ class Device : public Base bool dma_no_allocate; bool rx_thread; bool tx_thread; + bool rss; }; protected: diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh index fc1f4c06b..f90432398 100644 --- a/dev/sinicreg.hh +++ b/dev/sinicreg.hh @@ -81,6 +81,7 @@ __SINIC_REG32(HwAddr, 0x60); // 64: mac address __SINIC_REG32(Size, 0x68); // register addres space size // Config register bits +__SINIC_VAL32(Config_RSS, 10, 1); // enable receive side scaling __SINIC_VAL32(Config_RxThread, 9, 1); // enable receive threads __SINIC_VAL32(Config_TxThread, 8, 1); // enable transmit thread __SINIC_VAL32(Config_Filter, 7, 1); // enable receive filter -- cgit v1.2.3 From 0bf25c595364f7ca9b5e632c84fcf0d35dc3490a Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 3 Mar 2006 14:24:15 -0500 Subject: First cut at moving alpha specefic stuff out of /sim/system* into arch/alpha/system*. SConscript: dev/alpha_console.cc: dev/alpha_console.hh: kern/freebsd/freebsd_system.cc: kern/freebsd/freebsd_system.hh: kern/kernel_stats.cc: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/pseudo_inst.cc: sim/system.cc: sim/system.hh: First cut at moving alpha specefic stuff out of /sim/system* --HG-- extra : convert_revision : eba58f537fc04e605af4fc216e184b074a44c8a0 --- dev/alpha_console.cc | 6 +++--- dev/alpha_console.hh | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'dev') diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 2e8bbd1dd..94f834b4f 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -34,6 +34,7 @@ #include #include +#include "arch/alpha/system.hh" #include "base/inifile.hh" #include "base/str.hh" #include "base/trace.hh" @@ -50,13 +51,12 @@ #include "mem/functional/physical.hh" #include "sim/builder.hh" #include "sim/sim_object.hh" -#include "sim/system.hh" using namespace std; using namespace AlphaISA; AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d, - System *s, BaseCPU *c, Platform *p, + AlphaSystem *s, BaseCPU *c, Platform *p, MemoryController *mmu, Addr a, HierParams *hier, Bus *pio_bus) : PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a) @@ -323,7 +323,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) SimObjectParam disk; SimObjectParam mmu; Param addr; - SimObjectParam system; + SimObjectParam system; SimObjectParam cpu; SimObjectParam platform; SimObjectParam pio_bus; diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh index 2d1c1e634..86ef021e9 100644 --- a/dev/alpha_console.hh +++ b/dev/alpha_console.hh @@ -41,7 +41,7 @@ class BaseCPU; class SimConsole; -class System; +class AlphaSystem; class SimpleDisk; /** @@ -90,7 +90,7 @@ class AlphaConsole : public PioDevice SimConsole *console; /** a pointer to the system we are running in */ - System *system; + AlphaSystem *system; /** a pointer to the CPU boot cpu */ BaseCPU *cpu; @@ -101,7 +101,7 @@ class AlphaConsole : public PioDevice public: /** Standard Constructor */ AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d, - System *s, BaseCPU *c, Platform *platform, + AlphaSystem *s, BaseCPU *c, Platform *platform, MemoryController *mmu, Addr addr, HierParams *hier, Bus *pio_bus); -- cgit v1.2.3 From f15e492375e8ecd42a1f0ba7ead68cfeb2b4b673 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sat, 4 Mar 2006 15:18:40 -0500 Subject: Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. The major change is renaming the old ExecContext to CPUExecContext, and creating two new classes, ExecContext (an abstract class), and ProxyExecContext (a templated class that derives from ExecContext). Code outside of the CPU continues to use ExecContext as normal (other than not being able to access variables within the XC). The CPU uses the CPUExecContext, or however else it stores its own state. It then creates a ProxyExecContext, templated on the class used to hold its state. This proxy is passed to any code outside of the CPU that needs to access the XC. This allows code outside of the CPU to use the ExecContext interface to access any state needed, without knowledge of how that state is laid out. Note that these changes will not compile without the accompanying revision to automatically rename the shadow registers. SConscript: Include new file, cpu_exec_context.cc. arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_memory.cc: arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: arch/alpha/isa/decoder.isa: arch/alpha/stacktrace.cc: arch/alpha/vtophys.cc: base/remote_gdb.cc: cpu/intr_control.cc: Avoid directly accessing objects within the XC. arch/alpha/ev5.cc: Avoid directly accessing objects within the XC. KernelStats have been moved to the BaseCPU instead of the XC. arch/alpha/isa_traits.hh: Remove clearIprs(). It wasn't used very often and it did not work well with the proxy ExecContext. cpu/base.cc: Place kernel stats within the BaseCPU instead of the ExecContext. For now comment out the profiling code sampling until its exact location is decided upon. cpu/base.hh: Kernel stats are now in the BaseCPU instead of the ExecContext. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. cpu/exetrace.cc: Remove unneeded include of exec_context.hh. cpu/intr_control.hh: cpu/o3/alpha_cpu_builder.cc: Remove unneeded include of exec_context.hh cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. Also avoid accessing anything directly from the XC. cpu/pc_event.cc: Avoid accessing objects directly from the XC. dev/tsunami_cchip.cc: Avoid accessing objects directly within the XC> kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/linux/linux_threadinfo.hh: kern/tru64/dump_mbuf.cc: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: sim/syscall_emul.cc: sim/syscall_emul.hh: Avoid accessing objects directly within the XC. kern/kernel_stats.cc: kern/kernel_stats.hh: Kernel stats no longer exist within the XC. kern/system_events.cc: Avoid accessing objects directly within the XC. Also kernel stats are now in the BaseCPU. sim/process.cc: sim/process.hh: Avoid accessing regs directly within an ExecContext. Instead use a CPUExecContext to initialize the registers and copy them over. cpu/cpu_exec_context.cc: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. cpu/cpu_exec_context.hh: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. Remove kernel stats from the ExecContext. sim/pseudo_inst.cc: Kernel stats now live within the CPU. Avoid accessing objects directly within the XC. --HG-- rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : a75393a8945c80cca225b5e9d9c22a16609efb85 --- dev/tsunami_cchip.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'dev') diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 4dc4413a1..d311df4f5 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -113,7 +113,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) case TSDEV_CC_MISC: *(uint64_t*)data = (ipint << 8) & 0xF | (itint << 4) & 0xF | - (xc->cpu_id & 0x3); + (xc->readCpuId() & 0x3); return NoFault; case TSDEV_CC_AAR0: case TSDEV_CC_AAR1: -- cgit v1.2.3 From 11aead894d4186916b587b1449075f276319a235 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 7 Mar 2006 19:59:12 -0500 Subject: Updates for the quiesceEvent that was added to the XC. Also several files need to include system.hh or symtab.hh. This is because exec_context.hh has less #includes than before, requiring some of the files that include it to include some other files as well. arch/alpha/faults.cc: Avoid accessing XC directly. arch/alpha/stacktrace.cc: StackTrace needs to include system.hh. cpu/cpu_exec_context.cc: Update for change to CPUExecContext. cpu/cpu_exec_context.hh: Make quiesce events use CPUExecContext instead of ExecContext. Include functions to allow the quiesce event and last activate/suspend be accessed. cpu/exec_context.hh: Include functions for quiesceEvent. cpu/intr_control.cc: Needs to include cpu/exec_context.hh. cpu/profile.cc: Needs to include symtab.hh for the symbol table. cpu/profile.hh: Needs forward declare of ExecContext. cpu/simple/cpu.cc: Rename xc to cpuXC. dev/tsunami_cchip.cc: Needs to include exec_context.hh. kern/kernel_stats.cc: Needs to include system.hh. kern/linux/events.cc: Needs to include system.hh. Also avoid accessing objects directly from the XC. kern/tru64/dump_mbuf.cc: Include symtab.hh for the SymbolTable and system.hh. kern/tru64/tru64_events.cc: Include system.hh sim/pseudo_inst.cc: Avoid accessing objects directly within the XC. --HG-- extra : convert_revision : 78fe30d98cd20f7403fa216f772071458b675c84 --- dev/tsunami_cchip.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'dev') diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index d311df4f5..2649fe27a 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -42,6 +42,7 @@ #include "mem/bus/pio_interface.hh" #include "mem/bus/pio_interface_impl.hh" #include "mem/functional/memory_control.hh" +#include "cpu/exec_context.hh" #include "cpu/intr_control.hh" #include "sim/builder.hh" #include "sim/system.hh" -- cgit v1.2.3 From b5638330751f87930d61743030979e251cacd4ad Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 7 Mar 2006 22:56:12 -0500 Subject: Needs forward declaration of MemoryController. --HG-- extra : convert_revision : 07f397742a026cb6320dc29722d1db21157f26fa --- dev/baddev.hh | 2 ++ dev/isa_fake.hh | 2 ++ 2 files changed, 4 insertions(+) (limited to 'dev') diff --git a/dev/baddev.hh b/dev/baddev.hh index c2a204c05..189f28331 100644 --- a/dev/baddev.hh +++ b/dev/baddev.hh @@ -37,6 +37,8 @@ #include "base/range.hh" #include "dev/io_device.hh" +class MemoryController; + /** * BadDevice * This device just panics when accessed. It is supposed to warn diff --git a/dev/isa_fake.hh b/dev/isa_fake.hh index 290b24b54..73e40c681 100644 --- a/dev/isa_fake.hh +++ b/dev/isa_fake.hh @@ -37,6 +37,8 @@ #include "base/range.hh" #include "dev/io_device.hh" +class MemoryController; + /** * IsaFake is a device that returns -1 on all reads and * accepts all writes. It is meant to be placed at an address range -- cgit v1.2.3 From 4d44e53736507de176e48cbf99b064ffa0ae5a7a Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 8 Mar 2006 11:34:41 -0500 Subject: Forward declaration of MemoryController. My change to exec_context.hh probably affected these files to no longer have MemoryController forward declared through a long chain of includes. MemoryController should be forward declared where it is used anyways. dev/alpha_console.hh: dev/uart.hh: dev/uart8250.hh: Forward declaration of MemoryController. --HG-- extra : convert_revision : afaac4014e0eb3b6d5d385cd4444b77511e03b51 --- dev/alpha_console.hh | 1 + dev/uart.hh | 1 + dev/uart8250.hh | 1 + 3 files changed, 3 insertions(+) (limited to 'dev') diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh index 86ef021e9..f63c6ad7e 100644 --- a/dev/alpha_console.hh +++ b/dev/alpha_console.hh @@ -43,6 +43,7 @@ class BaseCPU; class SimConsole; class AlphaSystem; class SimpleDisk; +class MemoryController; /** * Memory mapped interface to the system console. This device diff --git a/dev/uart.hh b/dev/uart.hh index 145b9ca9e..78b1dc68e 100644 --- a/dev/uart.hh +++ b/dev/uart.hh @@ -37,6 +37,7 @@ #include "dev/io_device.hh" class SimConsole; +class MemoryController; class Platform; const int RX_INT = 0x1; diff --git a/dev/uart8250.hh b/dev/uart8250.hh index 88abf8e24..63d1da3cf 100644 --- a/dev/uart8250.hh +++ b/dev/uart8250.hh @@ -53,6 +53,7 @@ #define IIR_LINE 0x06 /* Rx Line Status (highest priority)*/ class SimConsole; +class MemoryController; class Platform; class Uart8250 : public Uart -- cgit v1.2.3