From f05cb84ed1a61f81c26e4ea22f98454d12f069aa Mon Sep 17 00:00:00 2001 From: Curtis Dunham Date: Wed, 8 Apr 2015 15:56:06 -0500 Subject: ext: Add SST connector This patch adds a connector that allows gem5 to be used as a component in SST (Structural Simulation Toolkit, sst-simulator.org). At a high level, this allows memory traffic to pass between the two simulators. SST Links are roughly analogous to gem5 Ports, although Links do not have a notion of master and slave. This distinction is important to gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave must be used, and similarly when connecting the memory side of SST cache to a gem5 port (for memory <-> I/O), an ExternalMaster must be used. These connectors handle the administrative aspects of gem5 (initialization, simulation, shutdown) as well as translating SST's MemEvents into gem5 Packets and vice-versa. --- ext/sst/LICENSE | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 ext/sst/LICENSE (limited to 'ext/sst/LICENSE') diff --git a/ext/sst/LICENSE b/ext/sst/LICENSE new file mode 100644 index 000000000..787cadce8 --- /dev/null +++ b/ext/sst/LICENSE @@ -0,0 +1,72 @@ +** This license only applies to the source files in this directory. + +Copyright (c) 2015 ARM Limited +All rights reserved. + +The license below extends only to copyright in the software and shall +not be construed as granting a license to any other intellectual +property including but not limited to intellectual property relating +to a hardware implementation of the functionality of the software +licensed hereunder. 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