From 86777c9db174c74be49667bce3dda99f8ba23696 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 18 May 2006 22:54:19 -0400 Subject: First steps toward getting full system to work with TimingSimpleCPU. Not there yet. cpu/simple/atomic.cc: Only read SC result if store was an SC. Don't fake SC here; fake it in PhysicalMemory so all CPU models can share in the joy. cpu/simple/timing.cc: Don't forget to checkForInterrupts(). Only fetch subsequent instruction if we're still running (i.e. not quiesced). dev/io_device.hh: Initialize port pointer in SendEvent object. mem/physical.cc: Move fake SC "implementation" here from AtomicSimpleCPU. mem/request.hh: Initialize flags to all clear, not uninitialized. Otherwise we can't reliably look at flags w/o explicitly setting them every time we create a request. --HG-- extra : convert_revision : ae7601ce6fb54c54e19848aa5391327f9a6e61a6 --- mem/physical.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'mem/physical.cc') diff --git a/mem/physical.cc b/mem/physical.cc index 8de9c3203..bc2500678 100644 --- a/mem/physical.cc +++ b/mem/physical.cc @@ -155,6 +155,11 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt) case Write: memcpy(pmem_addr + pkt->addr - base_addr, pkt->getPtr(), pkt->size); + // temporary hack: will need to add real LL/SC implementation + // for cacheless systems later. + if (pkt->req->getFlags() & LOCKED) { + pkt->req->setScResult(1); + } break; default: panic("unimplemented"); -- cgit v1.2.3