From 4f430e9ab56443e822171b7881f4d50475dbaf25 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Mon, 10 Apr 2006 12:23:17 -0400 Subject: Finally MIPS does hello world! arch/mips/isa/bitfields.isa: add RS_SRL bitfield ...these must be set to 0 for a SRL instruction arch/mips/isa/decoder.isa: Make unimplemented instructions Fail instead of just Warn Edits to SRA & SRAV instructions Implement CFC1 instructions Unaligned Memory Access Support (Maybe Not fully functional yet) Enforce a more strict decode policy (in terms of different bitfields set to 0 on certain instructions) arch/mips/isa/formats/branch.isa: Fix disassembly arch/mips/isa/formats/int.isa: Add sign extend Immediate and zero extend Immediate to Int class. Probably a bit unnecessary in the long run since these manipulations could be done in the actually instruction instead of keep a int value arch/mips/isa/formats/mem.isa: Comment/Remove out split-memory access code... revisit this after SimpleCPU works arch/mips/isa/formats/unimp.isa: Add inst2string function to Unimplemented panic. PRints out the instruction binary to help in debuggin arch/mips/isa/formats/unknown.isa: define inst2string function , use in unknown disassembly and panic function arch/mips/isa/operands.isa: Make "Mem" default to a unsigned word since this is MIPS32 arch/mips/isa_traits.hh: change return values to 32 instead of 64 arch/mips/linux_process.cc: assign some syscalls to the right functions cpu/static_inst.hh: more debug functions for MIPS (these will be move to the mips directory soon) mem/page_table.cc: mem/page_table.hh: toward a better implementation for unaligned memory access mem/request.hh: NO ALIGN FAULT flag added to support unaligned memory access sim/syscall_emul.cc: additional SyscallVerbose comments --HG-- extra : convert_revision : 1987d80c9f4ede507f1f0148435e0bee97d2428c --- mem/page_table.cc | 8 ++++---- mem/page_table.hh | 2 +- mem/request.hh | 2 ++ 3 files changed, 7 insertions(+), 5 deletions(-) (limited to 'mem') diff --git a/mem/page_table.cc b/mem/page_table.cc index 714ddde35..eb2c7cdbb 100644 --- a/mem/page_table.cc +++ b/mem/page_table.cc @@ -58,7 +58,7 @@ PageTable::~PageTable() } Fault -PageTable::page_check(Addr addr, int size) const +PageTable::page_check(Addr addr, int size, uint32_t flags) const { if (size < sizeof(uint64_t)) { if (!isPowerOf2(size)) { @@ -66,7 +66,7 @@ PageTable::page_check(Addr addr, int size) const return genMachineCheckFault(); } - if ((size - 1) & addr) + if (((size - 1) & addr) && (flags & NO_ALIGN_FAULT == 0)) return genAlignmentFault(); } else { @@ -75,7 +75,7 @@ PageTable::page_check(Addr addr, int size) const return genMachineCheckFault(); } - if ((sizeof(uint64_t) - 1) & addr) + if (((sizeof(uint64_t) - 1) & addr) && (flags & NO_ALIGN_FAULT == 0)) return genAlignmentFault(); } @@ -127,5 +127,5 @@ PageTable::translate(CpuRequestPtr &req) if (!translate(req->vaddr, req->paddr)) { return genMachineCheckFault(); } - return page_check(req->paddr, req->size); + return page_check(req->paddr, req->size, req->flags); } diff --git a/mem/page_table.hh b/mem/page_table.hh index 8f0842f58..66cce7cd6 100644 --- a/mem/page_table.hh +++ b/mem/page_table.hh @@ -67,7 +67,7 @@ class PageTable Addr pageAlign(Addr a) { return (a & ~offsetMask); } Addr pageOffset(Addr a) { return (a & offsetMask); } - Fault page_check(Addr addr, int size) const; + Fault page_check(Addr addr, int size, uint32_t flags) const; void allocate(Addr vaddr, int size); diff --git a/mem/request.hh b/mem/request.hh index 5e2275741..4b4703a0b 100644 --- a/mem/request.hh +++ b/mem/request.hh @@ -58,6 +58,8 @@ const unsigned NO_FAULT = 0x020; const unsigned PF_EXCLUSIVE = 0x100; /** The request should be marked as LRU. */ const unsigned EVICT_NEXT = 0x200; +/** The request should ignore unaligned access faults */ +const unsigned NO_ALIGN_FAULT = 0x400; class Request { -- cgit v1.2.3