From cf05fa476df711f64d0481117cf075ce68676d57 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 11 Mar 2005 18:28:38 -0500 Subject: stick all python stuff into a top level python directory. create an m5 package in python/m5 move the objects package into the m5 package move the m5config into the m5 package as config leave both importers outside of the package. SConscript: sim/main.cc: move sim/pyconfig/* -> python python/SConscript: m5config.py -> m5/config.py (now automatically embedded) objects -> python/m5/objects embed all python files in python/m5 python/m5/config.py: importer renamed mpy_importer move code to m5/__init__.py test/genini.py: deal with new python organization keep track of paths we want to add and add them after parameters are parsed. --HG-- rename : sim/pyconfig/SConscript => python/SConscript rename : sim/pyconfig/m5config.py => python/m5/config.py rename : objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.mpy rename : objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.mpy rename : objects/BadDevice.mpy => python/m5/objects/BadDevice.mpy rename : objects/BaseCPU.mpy => python/m5/objects/BaseCPU.mpy rename : objects/BaseCache.mpy => python/m5/objects/BaseCache.mpy rename : objects/BaseSystem.mpy => python/m5/objects/BaseSystem.mpy rename : objects/Bus.mpy => python/m5/objects/Bus.mpy rename : objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.mpy rename : objects/Device.mpy => python/m5/objects/Device.mpy rename : objects/DiskImage.mpy => python/m5/objects/DiskImage.mpy rename : objects/Ethernet.mpy => python/m5/objects/Ethernet.mpy rename : objects/Ide.mpy => python/m5/objects/Ide.mpy rename : objects/IntrControl.mpy => python/m5/objects/IntrControl.mpy rename : objects/MemTest.mpy => python/m5/objects/MemTest.mpy rename : objects/Pci.mpy => python/m5/objects/Pci.mpy rename : objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.mpy rename : objects/Platform.mpy => python/m5/objects/Platform.mpy rename : objects/Process.mpy => python/m5/objects/Process.mpy rename : objects/Repl.mpy => python/m5/objects/Repl.mpy rename : objects/Root.mpy => python/m5/objects/Root.mpy rename : objects/SimConsole.mpy => python/m5/objects/SimConsole.mpy rename : objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.mpy rename : objects/Tsunami.mpy => python/m5/objects/Tsunami.mpy rename : objects/Uart.mpy => python/m5/objects/Uart.mpy extra : convert_revision : aebf6ccda33028b1125974ca8b6aeab6f7570f30 --- objects/AlphaConsole.mpy | 9 ----- objects/AlphaTLB.mpy | 12 ------ objects/BadDevice.mpy | 5 --- objects/BaseCPU.mpy | 25 ------------- objects/BaseCache.mpy | 38 ------------------- objects/BaseSystem.mpy | 15 -------- objects/Bus.mpy | 6 --- objects/CoherenceProtocol.mpy | 6 --- objects/Device.mpy | 33 ----------------- objects/DiskImage.mpy | 14 ------- objects/Ethernet.mpy | 86 ------------------------------------------- objects/Ide.mpy | 14 ------- objects/IntrControl.mpy | 3 -- objects/MemTest.mpy | 18 --------- objects/Pci.mpy | 52 -------------------------- objects/PhysicalMemory.mpy | 7 ---- objects/Platform.mpy | 5 --- objects/Process.mpy | 15 -------- objects/Repl.mpy | 9 ----- objects/Root.mpy | 15 -------- objects/SimConsole.mpy | 11 ------ objects/SimpleDisk.mpy | 4 -- objects/Tsunami.mpy | 25 ------------- objects/Uart.mpy | 6 --- 24 files changed, 433 deletions(-) delete mode 100644 objects/AlphaConsole.mpy delete mode 100644 objects/AlphaTLB.mpy delete mode 100644 objects/BadDevice.mpy delete mode 100644 objects/BaseCPU.mpy delete mode 100644 objects/BaseCache.mpy delete mode 100644 objects/BaseSystem.mpy delete mode 100644 objects/Bus.mpy delete mode 100644 objects/CoherenceProtocol.mpy delete mode 100644 objects/Device.mpy delete mode 100644 objects/DiskImage.mpy delete mode 100644 objects/Ethernet.mpy delete mode 100644 objects/Ide.mpy delete mode 100644 objects/IntrControl.mpy delete mode 100644 objects/MemTest.mpy delete mode 100644 objects/Pci.mpy delete mode 100644 objects/PhysicalMemory.mpy delete mode 100644 objects/Platform.mpy delete mode 100644 objects/Process.mpy delete mode 100644 objects/Repl.mpy delete mode 100644 objects/Root.mpy delete mode 100644 objects/SimConsole.mpy delete mode 100644 objects/SimpleDisk.mpy delete mode 100644 objects/Tsunami.mpy delete mode 100644 objects/Uart.mpy (limited to 'objects') diff --git a/objects/AlphaConsole.mpy b/objects/AlphaConsole.mpy deleted file mode 100644 index 79918a01e..000000000 --- a/objects/AlphaConsole.mpy +++ /dev/null @@ -1,9 +0,0 @@ -from Device import PioDevice - -simobj AlphaConsole(PioDevice): - type = 'AlphaConsole' - cpu = Param.BaseCPU(Super, "Processor") - disk = Param.SimpleDisk("Simple Disk") - num_cpus = Param.Int(1, "Number of CPUs") - sim_console = Param.SimConsole(Super, "The Simulator Console") - system = Param.BaseSystem(Super, "system object") diff --git a/objects/AlphaTLB.mpy b/objects/AlphaTLB.mpy deleted file mode 100644 index 8e7cd62cc..000000000 --- a/objects/AlphaTLB.mpy +++ /dev/null @@ -1,12 +0,0 @@ -simobj AlphaTLB(SimObject): - type = 'AlphaTLB' - abstract = True - size = Param.Int("TLB size") - -simobj AlphaDTB(AlphaTLB): - type = 'AlphaDTB' - size = 64 - -simobj AlphaITB(AlphaTLB): - type = 'AlphaITB' - size = 48 diff --git a/objects/BadDevice.mpy b/objects/BadDevice.mpy deleted file mode 100644 index 35a12e0bf..000000000 --- a/objects/BadDevice.mpy +++ /dev/null @@ -1,5 +0,0 @@ -from Device import PioDevice - -simobj BadDevice(PioDevice): - type = 'BadDevice' - devicename = Param.String("Name of device to error on") diff --git a/objects/BaseCPU.mpy b/objects/BaseCPU.mpy deleted file mode 100644 index 484fcccd6..000000000 --- a/objects/BaseCPU.mpy +++ /dev/null @@ -1,25 +0,0 @@ -simobj BaseCPU(SimObject): - type = 'BaseCPU' - abstract = True - icache = Param.BaseMem(NULL, "L1 instruction cache object") - dcache = Param.BaseMem(NULL, "L1 data cache object") - - if Bool._convert(env.get('FULL_SYSTEM', 'False')): - dtb = Param.AlphaDTB("Data TLB") - itb = Param.AlphaITB("Instruction TLB") - mem = Param.FunctionalMemory("memory") - system = Param.BaseSystem(Super, "system object") - else: - workload = VectorParam.Process("processes to run") - - max_insts_all_threads = Param.Counter(0, - "terminate when all threads have reached this inst count") - max_insts_any_thread = Param.Counter(0, - "terminate when any thread reaches this inst count") - max_loads_all_threads = Param.Counter(0, - "terminate when all threads have reached this load count") - max_loads_any_thread = Param.Counter(0, - "terminate when any thread reaches this load count") - - defer_registration = Param.Bool(False, - "defer registration with system (for sampling)") diff --git a/objects/BaseCache.mpy b/objects/BaseCache.mpy deleted file mode 100644 index 98a422e30..000000000 --- a/objects/BaseCache.mpy +++ /dev/null @@ -1,38 +0,0 @@ -from BaseMem import BaseMem - -simobj BaseCache(BaseMem): - type = 'BaseCache' - adaptive_compression = Param.Bool(False, - "Use an adaptive compression scheme") - assoc = Param.Int("associativity") - block_size = Param.Int("block size in bytes") - compressed_bus = Param.Bool(False, - "This cache connects to a compressed memory") - compression_latency = Param.Int(0, - "Latency in cycles of compression algorithm") - do_copy = Param.Bool(False, "perform fast copies in the cache") - hash_delay = Param.Int(1, "time in cycles of hash access") - in_bus = Param.Bus(NULL, "incoming bus object") - lifo = Param.Bool(False, - "whether this NIC partition should use LIFO repl. policy") - max_miss_count = Param.Counter(0, - "number of misses to handle before calling exit") - mshrs = Param.Int("number of MSHRs (max outstanding requests)") - out_bus = Param.Bus("outgoing bus object") - prioritizeRequests = Param.Bool(False, - "always service demand misses first") - protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") - repl = Param.Repl(NULL, "replacement policy") - size = Param.Int("capacity in bytes") - split = Param.Bool(False, "whether or not this cache is split") - split_size = Param.Int(0, - "How many ways of the cache belong to CPU/LRU partition") - store_compressed = Param.Bool(False, - "Store compressed data in the cache") - subblock_size = Param.Int(0, - "Size of subblock in IIC used for compression") - tgts_per_mshr = Param.Int("max number of accesses per MSHR") - trace_addr = Param.Addr(0, "address to trace") - two_queue = Param.Bool(False, - "whether the lifo should have two queue replacement") - write_buffers = Param.Int(8, "number of write buffers") diff --git a/objects/BaseSystem.mpy b/objects/BaseSystem.mpy deleted file mode 100644 index 1cbdf4e99..000000000 --- a/objects/BaseSystem.mpy +++ /dev/null @@ -1,15 +0,0 @@ -simobj BaseSystem(SimObject): - type = 'BaseSystem' - abstract = True - memctrl = Param.MemoryController(Super, "memory controller") - physmem = Param.PhysicalMemory(Super, "phsyical memory") - kernel = Param.String("file that contains the kernel code") - console = Param.String("file that contains the console code") - pal = Param.String("file that contains palcode") - readfile = Param.String("", "file to read startup script from") - init_param = Param.UInt64(0, "numerical value to pass into simulator") - boot_osflags = Param.String("a", "boot flags to pass to the kernel") - system_type = Param.UInt64("Type of system we are emulating") - system_rev = Param.UInt64("Revision of system we are emulating") - bin = Param.Bool(False, "is this system binned") - binned_fns = VectorParam.String([], "functions broken down and binned") diff --git a/objects/Bus.mpy b/objects/Bus.mpy deleted file mode 100644 index 025d69785..000000000 --- a/objects/Bus.mpy +++ /dev/null @@ -1,6 +0,0 @@ -from BaseHier import BaseHier - -simobj Bus(BaseHier): - type = 'Bus' - clock_ratio = Param.Int("ratio of CPU to bus frequency") - width = Param.Int("bus width in bytes") diff --git a/objects/CoherenceProtocol.mpy b/objects/CoherenceProtocol.mpy deleted file mode 100644 index f3b0026b7..000000000 --- a/objects/CoherenceProtocol.mpy +++ /dev/null @@ -1,6 +0,0 @@ -class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi'] - -simobj CoherenceProtocol(SimObject): - type = 'CoherenceProtocol' - do_upgrades = Param.Bool(True, "use upgrade transactions?") - protocol = Param.Coherence("name of coherence protocol") diff --git a/objects/Device.mpy b/objects/Device.mpy deleted file mode 100644 index 47f8db1cb..000000000 --- a/objects/Device.mpy +++ /dev/null @@ -1,33 +0,0 @@ -from FunctionalMemory import FunctionalMemory - -# This device exists only because there are some devices that I don't -# want to have a Platform parameter because it would cause a cycle in -# the C++ that cannot be easily solved. -# -# The real solution to this problem is to pass the ParamXXX structure -# to the constructor, but with the express condition that SimObject -# parameter values are not to be available at construction time. If -# some further configuration must be done, it must be done during the -# initialization phase at which point all SimObject pointers will be -# valid. -simobj FooPioDevice(FunctionalMemory): - type = 'PioDevice' - abstract = True - addr = Param.Addr("Device Address") - mmu = Param.MemoryController(Super, "Memory Controller") - io_bus = Param.Bus(NULL, "The IO Bus to attach to") - pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles") - -simobj FooDmaDevice(FooPioDevice): - type = 'DmaDevice' - abstract = True - -simobj PioDevice(FooPioDevice): - type = 'PioDevice' - abstract = True - platform = Param.Platform(Super, "Platform") - -simobj DmaDevice(PioDevice): - type = 'DmaDevice' - abstract = True - diff --git a/objects/DiskImage.mpy b/objects/DiskImage.mpy deleted file mode 100644 index 80ef7b072..000000000 --- a/objects/DiskImage.mpy +++ /dev/null @@ -1,14 +0,0 @@ -simobj DiskImage(SimObject): - type = 'DiskImage' - abstract = True - image_file = Param.String("disk image file") - read_only = Param.Bool(False, "read only image") - -simobj RawDiskImage(DiskImage): - type = 'RawDiskImage' - -simobj CowDiskImage(DiskImage): - type = 'CowDiskImage' - child = Param.DiskImage("child image") - table_size = Param.Int(65536, "initial table size") - image_file = '' diff --git a/objects/Ethernet.mpy b/objects/Ethernet.mpy deleted file mode 100644 index 088df4b93..000000000 --- a/objects/Ethernet.mpy +++ /dev/null @@ -1,86 +0,0 @@ -from Device import DmaDevice -from Pci import PciDevice - -simobj EtherInt(SimObject): - type = 'EtherInt' - abstract = True - peer = Param.EtherInt(NULL, "peer interface") - -simobj EtherLink(SimObject): - type = 'EtherLink' - int1 = Param.EtherInt("interface 1") - int2 = Param.EtherInt("interface 2") - delay = Param.Tick(0, "transmit delay of packets in us") - speed = Param.Tick(100000000, "link speed in bits per second") - dump = Param.EtherDump(NULL, "dump object") - -simobj EtherBus(SimObject): - type = 'EtherBus' - loopback = Param.Bool(True, - "send packet back to the interface from which it came") - dump = Param.EtherDump(NULL, "dump object") - speed = Param.UInt64(100000000, "bus speed in bits per second") - -simobj EtherTap(EtherInt): - type = 'EtherTap' - bufsz = Param.Int(10000, "tap buffer size") - dump = Param.EtherDump(NULL, "dump object") - port = Param.UInt16(3500, "tap port") - -simobj EtherDump(SimObject): - type = 'EtherDump' - file = Param.String("dump file") - -simobj EtherDev(DmaDevice): - type = 'EtherDev' - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_read_delay = Param.Tick(0, "fixed delay for dma reads") - dma_read_factor = Param.Tick(0, "multiplier for dma reads") - dma_write_delay = Param.Tick(0, "fixed delay for dma writes") - dma_write_factor = Param.Tick(0, "multiplier for dma writes") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - rx_delay = Param.Tick(1000, "Receive Delay") - tx_delay = Param.Tick(1000, "Transmit Delay") - - intr_delay = Param.Tick(0, "Interrupt Delay in microseconds") - payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(Super, "Physical Memory") - tlaser = Param.Turbolaser(Super, "Turbolaser") - -simobj NSGigE(PciDevice): - type = 'NSGigE' - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_read_delay = Param.Tick(0, "fixed delay for dma reads") - dma_read_factor = Param.Tick(0, "multiplier for dma reads") - dma_write_delay = Param.Tick(0, "fixed delay for dma writes") - dma_write_factor = Param.Tick(0, "multiplier for dma writes") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - rx_delay = Param.Tick(1000, "Receive Delay") - tx_delay = Param.Tick(1000, "Transmit Delay") - - rx_fifo_size = Param.Int(131072, "max size in bytes of rxFifo") - tx_fifo_size = Param.Int(131072, "max size in bytes of txFifo") - - intr_delay = Param.Tick(0, "Interrupt Delay in microseconds") - payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(Super, "Physical Memory") - -simobj EtherDevInt(EtherInt): - type = 'EtherDevInt' - device = Param.EtherDev("Ethernet device of this interface") - -simobj NSGigEInt(EtherInt): - type = 'NSGigEInt' - device = Param.NSGigE("Ethernet device of this interface") - - diff --git a/objects/Ide.mpy b/objects/Ide.mpy deleted file mode 100644 index ce760ad96..000000000 --- a/objects/Ide.mpy +++ /dev/null @@ -1,14 +0,0 @@ -from Pci import PciDevice - -class IdeID(Enum): vals = ['master', 'slave'] - -simobj IdeDisk(SimObject): - type = 'IdeDisk' - delay = Param.Tick(1, "Fixed disk delay in microseconds") - driveID = Param.IdeID('master', "Drive ID") - image = Param.DiskImage("Disk image") - physmem = Param.PhysicalMemory(Super, "Physical memory") - -simobj IdeController(PciDevice): - type = 'IdeController' - disks = VectorParam.IdeDisk("IDE disks attached to this controller") diff --git a/objects/IntrControl.mpy b/objects/IntrControl.mpy deleted file mode 100644 index 1ef5a17ee..000000000 --- a/objects/IntrControl.mpy +++ /dev/null @@ -1,3 +0,0 @@ -simobj IntrControl(SimObject): - type = 'IntrControl' - cpu = Param.BaseCPU(Super, "the cpu") diff --git a/objects/MemTest.mpy b/objects/MemTest.mpy deleted file mode 100644 index af14ed9c3..000000000 --- a/objects/MemTest.mpy +++ /dev/null @@ -1,18 +0,0 @@ -simobj MemTest(SimObject): - type = 'MemTest' - cache = Param.BaseCache("L1 cache") - check_mem = Param.FunctionalMemory("check memory") - main_mem = Param.FunctionalMemory("hierarchical memory") - max_loads = Param.Counter("number of loads to execute") - memory_size = Param.Int(65536, "memory size") - percent_copies = Param.Percent(0, "target copy percentage") - percent_dest_unaligned = Param.Percent(50, - "percent of copy dest address that are unaligned") - percent_reads = Param.Percent(65, "target read percentage") - percent_source_unaligned = Param.Percent(50, - "percent of copy source address that are unaligned") - percent_uncacheable = Param.Percent(10, - "target uncacheable percentage") - progress_interval = Param.Counter(1000000, - "progress report interval (in accesses)") - trace_addr = Param.Addr(0, "address to trace") diff --git a/objects/Pci.mpy b/objects/Pci.mpy deleted file mode 100644 index caa3c52ff..000000000 --- a/objects/Pci.mpy +++ /dev/null @@ -1,52 +0,0 @@ -from Device import FooPioDevice, DmaDevice - -simobj PciConfigData(FooPioDevice): - type = 'PciConfigData' - addr = 0xffffffffffffffffL - VendorID = Param.UInt16("Vendor ID") - DeviceID = Param.UInt16("Device ID") - Command = Param.UInt16(0, "Command") - Status = Param.UInt16(0, "Status") - Revision = Param.UInt8(0, "Device") - ProgIF = Param.UInt8(0, "Programming Interface") - SubClassCode = Param.UInt8(0, "Sub-Class Code") - ClassCode = Param.UInt8(0, "Class Code") - CacheLineSize = Param.UInt8(0, "System Cacheline Size") - LatencyTimer = Param.UInt8(0, "PCI Latency Timer") - HeaderType = Param.UInt8(0, "PCI Header Type") - BIST = Param.UInt8(0, "Built In Self Test") - - BAR0 = Param.UInt32(0x00, "Base Address Register 0") - BAR1 = Param.UInt32(0x00, "Base Address Register 1") - BAR2 = Param.UInt32(0x00, "Base Address Register 2") - BAR3 = Param.UInt32(0x00, "Base Address Register 3") - BAR4 = Param.UInt32(0x00, "Base Address Register 4") - BAR5 = Param.UInt32(0x00, "Base Address Register 5") - BAR0Size = Param.UInt32(0, "Base Address Register 0 Size") - BAR1Size = Param.UInt32(0, "Base Address Register 1 Size") - BAR2Size = Param.UInt32(0, "Base Address Register 2 Size") - BAR3Size = Param.UInt32(0, "Base Address Register 3 Size") - BAR4Size = Param.UInt32(0, "Base Address Register 4 Size") - BAR5Size = Param.UInt32(0, "Base Address Register 5 Size") - - CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") - SubsystemID = Param.UInt16(0x00, "Subsystem ID") - SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") - ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") - InterruptLine = Param.UInt8(0x00, "Interrupt Line") - InterruptPin = Param.UInt8(0x00, "Interrupt Pin") - MaximumLatency = Param.UInt8(0x00, "Maximum Latency") - MinimumGrant = Param.UInt8(0x00, "Minimum Grant") - -simobj PciConfigAll(FooPioDevice): - type = 'PciConfigAll' - -simobj PciDevice(DmaDevice): - type = 'PciDevice' - abstract = True - pci_bus = Param.Int("PCI bus") - pci_dev = Param.Int("PCI device number") - pci_func = Param.Int("PCI function code") - configdata = Param.PciConfigData(Super, "PCI Config data") - configspace = Param.PciConfigAll(Super, "PCI Configspace") - addr = 0xffffffffffffffffL diff --git a/objects/PhysicalMemory.mpy b/objects/PhysicalMemory.mpy deleted file mode 100644 index d1e4ad4b4..000000000 --- a/objects/PhysicalMemory.mpy +++ /dev/null @@ -1,7 +0,0 @@ -from FunctionalMemory import FunctionalMemory - -simobj PhysicalMemory(FunctionalMemory): - type = 'PhysicalMemory' - range = Param.AddrRange("Device Address") - file = Param.String('', "memory mapped file") - mmu = Param.MemoryController(Super, "Memory Controller") diff --git a/objects/Platform.mpy b/objects/Platform.mpy deleted file mode 100644 index d0510eaf8..000000000 --- a/objects/Platform.mpy +++ /dev/null @@ -1,5 +0,0 @@ -simobj Platform(SimObject): - type = 'Platform' - abstract = True - interrupt_frequency = Param.Tick(1200, "frequency of interrupts") - intrctrl = Param.IntrControl(Super, "interrupt controller") diff --git a/objects/Process.mpy b/objects/Process.mpy deleted file mode 100644 index 6a91c09c2..000000000 --- a/objects/Process.mpy +++ /dev/null @@ -1,15 +0,0 @@ -simobj Process(SimObject): - type = 'Process' - abstract = True - output = Param.String('cout', 'filename for stdout/stderr') - -simobj LiveProcess(Process): - type = 'LiveProcess' - cmd = VectorParam.String("command line (executable plus arguments)") - env = VectorParam.String('', "environment settings") - input = Param.String('cin', "filename for stdin") - -simobj EioProcess(Process): - type = 'EioProcess' - chkpt = Param.String('', "EIO checkpoint file name (optional)") - file = Param.String("EIO trace file name") diff --git a/objects/Repl.mpy b/objects/Repl.mpy deleted file mode 100644 index fff5a2a02..000000000 --- a/objects/Repl.mpy +++ /dev/null @@ -1,9 +0,0 @@ -simobj Repl(SimObject): - type = 'Repl' - abstract = True - -simobj GenRepl(Repl): - type = 'GenRepl' - fresh_res = Param.Int("associativity") - num_pools = Param.Int("capacity in bytes") - pool_res = Param.Int("block size in bytes") diff --git a/objects/Root.mpy b/objects/Root.mpy deleted file mode 100644 index 0e531054b..000000000 --- a/objects/Root.mpy +++ /dev/null @@ -1,15 +0,0 @@ -from HierParams import HierParams -from Serialize import Serialize -from Statistics import Statistics -from Trace import Trace - -simobj Root(SimObject): - type = 'Root' - frequency = Param.Tick(200000000, "tick frequency") - output_file = Param.String('cout', "file to dump simulator output to") - full_system = Param.Bool("Full system simulation?") - hier = HierParams(do_data = False, do_events = True) - checkpoint = Param.String('', "Checkpoint file") - stats = Statistics() - trace = Trace() - serialize = Serialize() diff --git a/objects/SimConsole.mpy b/objects/SimConsole.mpy deleted file mode 100644 index fb74f1775..000000000 --- a/objects/SimConsole.mpy +++ /dev/null @@ -1,11 +0,0 @@ -simobj ConsoleListener(SimObject): - type = 'ConsoleListener' - port = Param.UInt16(3456, "listen port") - -simobj SimConsole(SimObject): - type = 'SimConsole' - append_name = Param.Bool(True, "append name() to filename") - intr_control = Param.IntrControl(Super, "interrupt controller") - listener = Param.ConsoleListener("console listener") - number = Param.Int(0, "console number") - output = Param.String('console', "file to dump output to") diff --git a/objects/SimpleDisk.mpy b/objects/SimpleDisk.mpy deleted file mode 100644 index c4dd5435b..000000000 --- a/objects/SimpleDisk.mpy +++ /dev/null @@ -1,4 +0,0 @@ -simobj SimpleDisk(SimObject): - type = 'SimpleDisk' - disk = Param.DiskImage("Disk Image") - physmem = Param.PhysicalMemory(Super, "Physical Memory") diff --git a/objects/Tsunami.mpy b/objects/Tsunami.mpy deleted file mode 100644 index cfe23977e..000000000 --- a/objects/Tsunami.mpy +++ /dev/null @@ -1,25 +0,0 @@ -from Device import FooPioDevice -from Platform import Platform - -simobj Tsunami(Platform): - type = 'Tsunami' - pciconfig = Param.PciConfigAll("PCI configuration") - system = Param.BaseSystem(Super, "system") - interrupt_frequency = Param.Int(1024, "frequency of interrupts") - -simobj TsunamiCChip(FooPioDevice): - type = 'TsunamiCChip' - tsunami = Param.Tsunami(Super, "Tsunami") - -simobj TsunamiFake(FooPioDevice): - type = 'TsunamiFake' - -simobj TsunamiIO(FooPioDevice): - type = 'TsunamiIO' - time = Param.UInt64(1136073600, - "System time to use (0 for actual time, default is 1/1/06)") - tsunami = Param.Tsunami(Super, "Tsunami") - -simobj TsunamiPChip(FooPioDevice): - type = 'TsunamiPChip' - tsunami = Param.Tsunami(Super, "Tsunami") diff --git a/objects/Uart.mpy b/objects/Uart.mpy deleted file mode 100644 index 76ee8805f..000000000 --- a/objects/Uart.mpy +++ /dev/null @@ -1,6 +0,0 @@ -from Device import PioDevice - -simobj Uart(PioDevice): - type = 'Uart' - console = Param.SimConsole(Super, "The console") - size = Param.Addr(0x8, "Device size") -- cgit v1.2.3