From 2d2f663d3aa993b5914cb27fab7c859fd4829001 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Fri, 8 Apr 2005 17:19:56 -0400 Subject: Add Parameter to only do prefetch calculations on data accesses not instruction accesses --HG-- extra : convert_revision : 85c987561a962f21466f0c1bd0473300d341c398 --- python/m5/objects/BaseCache.mpy | 2 ++ 1 file changed, 2 insertions(+) (limited to 'python/m5/objects/BaseCache.mpy') diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy index 214e0555c..a9bda5c99 100644 --- a/python/m5/objects/BaseCache.mpy +++ b/python/m5/objects/BaseCache.mpy @@ -58,3 +58,5 @@ simobj BaseCache(BaseMem): "Check if in cash on push or pop of prefetch queue") prefetch_use_cpu_id = Param.Bool(True, "Use the CPU ID to seperate calculations of prefetches") + prefetch_data_accesses_only = Param.Bool(False, + "Only prefetch on data not on instruction accesses") -- cgit v1.2.3 From 5eab6c4b414aef5801d825ab65c0e303a5bbe2e2 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 11 Apr 2005 15:32:06 -0400 Subject: Make the notion of a global event tick independent of the actual CPU cycle ticks. This allows the user to have CPUs of different frequencies, and also allows frequencies and latencies that are not evenly divisible by the CPU frequency. For now, the CPU frequency is still set to the global frequency, but soon, we'll hopefully make the global frequency fixed at something like 1THz and set all other frequencies independently. arch/alpha/ev5.cc: The cycles counter is based on the current cpu cycle. cpu/base_cpu.cc: frequency isn't the cpu parameter anymore, cycleTime is. cpu/base_cpu.hh: frequency isn't the cpu parameter anymore, cycleTime is. create several public functions for getting the cpu frequency and the numbers of ticks for a given number of cycles, etc. cpu/memtest/memtest.cc: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/trace/trace_cpu.cc: Now that ticks aren't cpu cycles, fixup code to advance by the proper number of ticks. cpu/memtest/memtest.hh: cpu/trace/trace_cpu.hh: Provide a function to get the number of ticks for a given number of cycles. dev/alpha_console.cc: Update for changes in the way that frequencies and latencies are accessed. Move some stuff to init() dev/alpha_console.hh: Need a pointer to the system and the cpu to get the frequency so we can pass the info to the console code. dev/etherbus.cc: dev/etherbus.hh: dev/etherlink.cc: dev/etherlink.hh: dev/ethertap.cc: dev/ide_disk.hh: dev/ns_gige.cc: dev/ns_gige.hh: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. dev/ide_disk.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. Add some extra debugging printfs dev/platform.cc: dev/sinic.cc: dev/sinic.hh: outline the constructor and destructor dev/platform.hh: outline the constructor and destructor. don't keep track of the interrupt frequency. Only provide the accessor function. dev/tsunami.cc: dev/tsunami.hh: outline the constructor and destructor Don't set the interrupt frequency here. Get it from the actual device that does the interrupting. dev/tsunami_io.cc: dev/tsunami_io.hh: Make the interrupt interval a configuration parameter. (And convert the interval to the new latency/frequency stuff in the python) kern/linux/linux_system.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. kern/tru64/tru64_system.cc: For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. python/m5/config.py: Fix support for cycle_time relative latencies and frequencies. Add support for getting a NetworkBandwidth or a MemoryBandwidth. python/m5/objects/BaseCPU.mpy: All CPUs now have a cycle_time. The default is the global frequency, but it is now possible to set the global frequency to some large value (like 1THz) and set each CPU frequency independently. python/m5/objects/BaseCache.mpy: python/m5/objects/Ide.mpy: Make this a Latency parameter python/m5/objects/BaseSystem.mpy: We need to pass the boot CPU's frequency to the system python/m5/objects/Ethernet.mpy: Update parameter types to use latency and bandwidth types python/m5/objects/Platform.mpy: this frequency isn't needed. We get it from the clock interrupt. python/m5/objects/Tsunami.mpy: The clock generator should hold the frequency sim/eventq.hh: Need to remove this assertion because the writeback event queue is different from the CPU's event queue which can cause this assertion to fail. sim/process.cc: Fix comment. sim/system.hh: Struct member to hold the boot CPU's frequency. sim/universe.cc: remove unneeded variable. --HG-- extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc --- python/m5/objects/BaseCache.mpy | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'python/m5/objects/BaseCache.mpy') diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy index a9bda5c99..da0c7c50e 100644 --- a/python/m5/objects/BaseCache.mpy +++ b/python/m5/objects/BaseCache.mpy @@ -10,7 +10,7 @@ simobj BaseCache(BaseMem): block_size = Param.Int("block size in bytes") compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") - compression_latency = Param.Int(0, + compression_latency = Param.Latency('0c', "Latency in cycles of compression algorithm") do_copy = Param.Bool(False, "perform fast copies in the cache") hash_delay = Param.Int(1, "time in cycles of hash access") -- cgit v1.2.3