From 8031cd93b53cd3fe17a5a5f21e8e8bd833398e97 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 1 Jun 2005 21:44:00 -0400 Subject: Standardize clock parameter names to 'clock'. Fix description for Bus clock_ratio (no longer a ratio). Add Clock param type (generic Frequency or Latency). cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/beta_cpu/alpha_full_cpu_builder.cc: cpu/simple_cpu/simple_cpu.cc: dev/ide_ctrl.cc: dev/ns_gige.cc: dev/ns_gige.hh: dev/pciconfigall.cc: dev/sinic.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: python/m5/objects/BaseCPU.py: python/m5/objects/BaseCache.py: python/m5/objects/BaseSystem.py: python/m5/objects/Bus.py: python/m5/objects/Ethernet.py: python/m5/objects/Root.py: sim/universe.cc: Standardize clock parameter names to 'clock'. Fix description for Bus clock_ratio (no longer a ratio). python/m5/config.py: Minor tweaks on Frequency/Latency: - added new Clock param type to avoid ambiguities - factored out init code into getLatency() - made RootFrequency *not* a subclass of Frequency so it can't be directly assigned to a Frequency paremeter --HG-- extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506 --- python/m5/objects/Ethernet.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'python/m5/objects/Ethernet.py') diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index 69dec1528..c89505477 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -58,7 +58,7 @@ class NSGigE(PciDevice): hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") - cycle_time = Param.Frequency('100MHz', "State machine processor frequency") + clock = Param.Clock('100MHz', "State machine processor frequency") dma_data_free = Param.Bool(False, "DMA of Data is free") dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") @@ -95,7 +95,7 @@ class Sinic(PciDevice): hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") - cycle_time = Param.Frequency('100MHz', "State machine processor frequency") + clock = Param.Clock('100MHz', "State machine processor frequency") dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") dma_read_factor = Param.Latency('0us', "multiplier for dma reads") -- cgit v1.2.3