From f806a25c9edb3a9a9f5bc34b88340be6b24a2022 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 21 Nov 2005 23:43:15 -0500 Subject: add support for delaying pio writes until the cache access occurs dev/ns_gige.cc: add support for delaying pio writes until the cache access occurs the only write we delay are for CR_TXE and CR_RXE dev/sinic.cc: dev/sinic.hh: the txPioRequest and rxPioRequest things were more or less bogus add support for delaying pio writes until the cache access occurs dev/sinicreg.hh: Add delay_read and delay_write to the register information struct for now, we won't delay any reads, and we'll delay the writes that initiate DMAs python/m5/objects/Ethernet.py: add a parameter to delay pio writes until the timing access actually occurs. --HG-- extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d --- python/m5/objects/Ethernet.py | 1 + 1 file changed, 1 insertion(+) (limited to 'python/m5/objects/Ethernet.py') diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index a2a8b217f..491ca4d9f 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -76,6 +76,7 @@ class EtherDevBase(PciDevice): dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") dma_write_factor = Param.Latency('0us', "multiplier for dma writes") dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") + pio_delay_write = Param.Bool(False, "Delay pio writes until timing occurs") rx_delay = Param.Latency('1us', "Receive Delay") tx_delay = Param.Latency('1us', "Transmit Delay") -- cgit v1.2.3