From 716ceb6c107751fded501f18466a4166b7809e64 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 11 Aug 2006 17:42:59 -0400 Subject: Code update for CPU models. arch/alpha/isa_traits.hh: Add in clear functions. cpu/base.cc: cpu/base.hh: Add in CPU progress event. cpu/base_dyn_inst.hh: Mimic normal registers in terms of writing/reading floats. cpu/checker/cpu.cc: cpu/checker/cpu.hh: cpu/checker/cpu_builder.cc: cpu/checker/o3_cpu_builder.cc: Fix up stuff. cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: Bring up to speed with newmem. cpu/o3/alpha_cpu_builder.cc: Allow for progress intervals. cpu/o3/tournament_pred.cc: Fix up predictor. cpu/o3/tournament_pred.hh: cpu/ozone/cpu.hh: cpu/ozone/cpu_impl.hh: cpu/simple/cpu.cc: Fixes. cpu/ozone/cpu_builder.cc: Allow progress interval. cpu/ozone/front_end_impl.hh: Comment out this message. cpu/ozone/lw_back_end_impl.hh: Remove this. python/m5/objects/BaseCPU.py: Add progress interval. python/m5/objects/Root.py: Allow for stat reset. sim/serialize.cc: sim/stat_control.cc: Add in stats reset. --HG-- extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e --- python/m5/objects/Root.py | 2 ++ 1 file changed, 2 insertions(+) (limited to 'python/m5/objects/Root.py') diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py index 23b13fc67..0973d6ae5 100644 --- a/python/m5/objects/Root.py +++ b/python/m5/objects/Root.py @@ -1,6 +1,7 @@ from m5 import * from HierParams import HierParams from Serialize import Serialize +from Serialize import Statreset from Statistics import Statistics from Trace import Trace from ExeTrace import ExecutionTrace @@ -23,3 +24,4 @@ class Root(SimObject): trace = Trace() exetrace = ExecutionTrace() serialize = Serialize() + statsreset = Statreset() -- cgit v1.2.3