From 935ba67b4fbe595c0496e0230e39cd8ed87b7543 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Wed, 17 May 2006 22:08:44 -0400
Subject: Get basic full-system working with AtomicSimpleCPU.

SConscript:
    Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
    Fix paths.
configs/test/fs.py:
    SimpleCPU -> AtomicSimpleCPU
    Fix vmlinux path
cpu/simple/atomic.cc:
    Fix suspendContext() so quiesce works.
    Don't forget to checkForInterrupts().
cpu/simple/base.cc:
    Minor fix to interrupt check code.
dev/ide_disk.hh:
    Don't declare regStats() in header since it's not in
    .cc file anymore (will need to add it back in when
    stats are added back).
dev/io_device.cc:
    Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
    Set PCI config packet result to Success.
python/m5/objects/Root.py:
    Add debug object to Root so things like break_cycles
    can be set from command line.

--HG--
extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
---
 python/m5/objects/Root.py | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'python/m5/objects/Root.py')

diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py
index f51516098..205a93c76 100644
--- a/python/m5/objects/Root.py
+++ b/python/m5/objects/Root.py
@@ -3,6 +3,7 @@ from Serialize import Serialize
 from Statistics import Statistics
 from Trace import Trace
 from ExeTrace import ExecutionTrace
+from Debug import Debug
 
 class Root(SimObject):
     type = 'Root'
@@ -19,3 +20,4 @@ class Root(SimObject):
     trace = Trace()
     exetrace = ExecutionTrace()
     serialize = Serialize()
+    debug = Debug()
-- 
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