From aad02f80880c1b88b8f4feaa605653953848b7c3 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sun, 29 May 2005 01:14:50 -0400 Subject: Major cleanup of python config code. Special mpy importer is gone; everything is just plain Python now (funky, but straight-up). May not completely work yet... generates identical ini files for many configs/kernel settings, but I have yet to run it against regressions. This commit is for my own convenience and won't be pushed until more testing is done. python/m5/__init__.py: Get rid of mpy_importer and param_types. python/m5/config.py: Major cleanup. We now have separate classes and instances for SimObjects. Proxy handling and param conversion significantly reorganized. No explicit instantiation step anymore; we can dump an ini file straight from the original tree. Still needs more/better/truer comments. test/genini.py: Replace LoadMpyFile() with built-in execfile(). Export __main__.m5_build_env. python/m5/objects/AlphaConsole.py: python/m5/objects/AlphaFullCPU.py: python/m5/objects/AlphaTLB.py: python/m5/objects/BadDevice.py: python/m5/objects/BaseCPU.py: python/m5/objects/BaseCache.py: python/m5/objects/BaseSystem.py: python/m5/objects/Bus.py: python/m5/objects/CoherenceProtocol.py: python/m5/objects/Device.py: python/m5/objects/DiskImage.py: python/m5/objects/Ethernet.py: python/m5/objects/Ide.py: python/m5/objects/IntrControl.py: python/m5/objects/MemTest.py: python/m5/objects/Pci.py: python/m5/objects/PhysicalMemory.py: python/m5/objects/Platform.py: python/m5/objects/Process.py: python/m5/objects/Repl.py: python/m5/objects/Root.py: python/m5/objects/SimConsole.py: python/m5/objects/SimpleDisk.py: python/m5/objects/Tsunami.py: python/m5/objects/Uart.py: Fixes for eliminating mpy_importer, and modified handling of frequency/latency params. Also renamed parent to Parent. --HG-- rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76 --- python/m5/objects/AlphaConsole.mpy | 9 --- python/m5/objects/AlphaConsole.py | 10 +++ python/m5/objects/AlphaFullCPU.mpy | 79 --------------------- python/m5/objects/AlphaFullCPU.py | 80 +++++++++++++++++++++ python/m5/objects/AlphaTLB.mpy | 12 ---- python/m5/objects/AlphaTLB.py | 13 ++++ python/m5/objects/BadDevice.mpy | 5 -- python/m5/objects/BadDevice.py | 6 ++ python/m5/objects/BaseCPU.mpy | 27 ------- python/m5/objects/BaseCPU.py | 28 ++++++++ python/m5/objects/BaseCache.mpy | 64 ----------------- python/m5/objects/BaseCache.py | 65 +++++++++++++++++ python/m5/objects/BaseSystem.mpy | 17 ----- python/m5/objects/BaseSystem.py | 18 +++++ python/m5/objects/Bus.mpy | 6 -- python/m5/objects/Bus.py | 7 ++ python/m5/objects/CoherenceProtocol.mpy | 6 -- python/m5/objects/CoherenceProtocol.py | 7 ++ python/m5/objects/Device.mpy | 33 --------- python/m5/objects/Device.py | 34 +++++++++ python/m5/objects/DiskImage.mpy | 14 ---- python/m5/objects/DiskImage.py | 15 ++++ python/m5/objects/Ethernet.mpy | 121 ------------------------------- python/m5/objects/Ethernet.py | 122 ++++++++++++++++++++++++++++++++ python/m5/objects/Ide.mpy | 14 ---- python/m5/objects/Ide.py | 15 ++++ python/m5/objects/IntrControl.mpy | 3 - python/m5/objects/IntrControl.py | 4 ++ python/m5/objects/MemTest.mpy | 18 ----- python/m5/objects/MemTest.py | 19 +++++ python/m5/objects/Pci.mpy | 51 ------------- python/m5/objects/Pci.py | 52 ++++++++++++++ python/m5/objects/PhysicalMemory.mpy | 7 -- python/m5/objects/PhysicalMemory.py | 8 +++ python/m5/objects/Platform.mpy | 4 -- python/m5/objects/Platform.py | 5 ++ python/m5/objects/Process.mpy | 15 ---- python/m5/objects/Process.py | 16 +++++ python/m5/objects/Repl.mpy | 9 --- python/m5/objects/Repl.py | 10 +++ python/m5/objects/Root.mpy | 14 ---- python/m5/objects/Root.py | 20 ++++++ python/m5/objects/SimConsole.mpy | 11 --- python/m5/objects/SimConsole.py | 12 ++++ python/m5/objects/SimpleDisk.mpy | 4 -- python/m5/objects/SimpleDisk.py | 5 ++ python/m5/objects/Tsunami.mpy | 25 ------- python/m5/objects/Tsunami.py | 26 +++++++ python/m5/objects/Uart.mpy | 6 -- python/m5/objects/Uart.py | 7 ++ 50 files changed, 604 insertions(+), 574 deletions(-) delete mode 100644 python/m5/objects/AlphaConsole.mpy create mode 100644 python/m5/objects/AlphaConsole.py delete mode 100644 python/m5/objects/AlphaFullCPU.mpy create mode 100644 python/m5/objects/AlphaFullCPU.py delete mode 100644 python/m5/objects/AlphaTLB.mpy create mode 100644 python/m5/objects/AlphaTLB.py delete mode 100644 python/m5/objects/BadDevice.mpy create mode 100644 python/m5/objects/BadDevice.py delete mode 100644 python/m5/objects/BaseCPU.mpy create mode 100644 python/m5/objects/BaseCPU.py delete mode 100644 python/m5/objects/BaseCache.mpy create mode 100644 python/m5/objects/BaseCache.py delete mode 100644 python/m5/objects/BaseSystem.mpy create mode 100644 python/m5/objects/BaseSystem.py delete mode 100644 python/m5/objects/Bus.mpy create mode 100644 python/m5/objects/Bus.py delete mode 100644 python/m5/objects/CoherenceProtocol.mpy create mode 100644 python/m5/objects/CoherenceProtocol.py delete mode 100644 python/m5/objects/Device.mpy create mode 100644 python/m5/objects/Device.py delete mode 100644 python/m5/objects/DiskImage.mpy create mode 100644 python/m5/objects/DiskImage.py delete mode 100644 python/m5/objects/Ethernet.mpy create mode 100644 python/m5/objects/Ethernet.py delete mode 100644 python/m5/objects/Ide.mpy create mode 100644 python/m5/objects/Ide.py delete mode 100644 python/m5/objects/IntrControl.mpy create mode 100644 python/m5/objects/IntrControl.py delete mode 100644 python/m5/objects/MemTest.mpy create mode 100644 python/m5/objects/MemTest.py delete mode 100644 python/m5/objects/Pci.mpy create mode 100644 python/m5/objects/Pci.py delete mode 100644 python/m5/objects/PhysicalMemory.mpy create mode 100644 python/m5/objects/PhysicalMemory.py delete mode 100644 python/m5/objects/Platform.mpy create mode 100644 python/m5/objects/Platform.py delete mode 100644 python/m5/objects/Process.mpy create mode 100644 python/m5/objects/Process.py delete mode 100644 python/m5/objects/Repl.mpy create mode 100644 python/m5/objects/Repl.py delete mode 100644 python/m5/objects/Root.mpy create mode 100644 python/m5/objects/Root.py delete mode 100644 python/m5/objects/SimConsole.mpy create mode 100644 python/m5/objects/SimConsole.py delete mode 100644 python/m5/objects/SimpleDisk.mpy create mode 100644 python/m5/objects/SimpleDisk.py delete mode 100644 python/m5/objects/Tsunami.mpy create mode 100644 python/m5/objects/Tsunami.py delete mode 100644 python/m5/objects/Uart.mpy create mode 100644 python/m5/objects/Uart.py (limited to 'python/m5/objects') diff --git a/python/m5/objects/AlphaConsole.mpy b/python/m5/objects/AlphaConsole.mpy deleted file mode 100644 index 63aea5b7d..000000000 --- a/python/m5/objects/AlphaConsole.mpy +++ /dev/null @@ -1,9 +0,0 @@ -from Device import PioDevice - -simobj AlphaConsole(PioDevice): - type = 'AlphaConsole' - cpu = Param.BaseCPU(parent.any, "Processor") - disk = Param.SimpleDisk("Simple Disk") - num_cpus = Param.Int(1, "Number of CPUs") - sim_console = Param.SimConsole(parent.any, "The Simulator Console") - system = Param.BaseSystem(parent.any, "system object") diff --git a/python/m5/objects/AlphaConsole.py b/python/m5/objects/AlphaConsole.py new file mode 100644 index 000000000..9fe31b009 --- /dev/null +++ b/python/m5/objects/AlphaConsole.py @@ -0,0 +1,10 @@ +from m5 import * +from Device import PioDevice + +class AlphaConsole(PioDevice): + type = 'AlphaConsole' + cpu = Param.BaseCPU(Parent.any, "Processor") + disk = Param.SimpleDisk("Simple Disk") + num_cpus = Param.Int(1, "Number of CPUs") + sim_console = Param.SimConsole(Parent.any, "The Simulator Console") + system = Param.BaseSystem(Parent.any, "system object") diff --git a/python/m5/objects/AlphaFullCPU.mpy b/python/m5/objects/AlphaFullCPU.mpy deleted file mode 100644 index bf3f2d718..000000000 --- a/python/m5/objects/AlphaFullCPU.mpy +++ /dev/null @@ -1,79 +0,0 @@ -from BaseCPU import BaseCPU - -simobj DerivAlphaFullCPU(BaseCPU): - type = 'DerivAlphaFullCPU' - - numThreads = Param.Unsigned("number of HW thread contexts") - - if not build_env['FULL_SYSTEM']: - mem = Param.FunctionalMemory(NULL, "memory") - - decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") - renameToFetchDelay = Param.Unsigned("Rename to fetch delay") - iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " - "delay") - commitToFetchDelay = Param.Unsigned("Commit to fetch delay") - fetchWidth = Param.Unsigned("Fetch width") - - renameToDecodeDelay = Param.Unsigned("Rename to decode delay") - iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " - "delay") - commitToDecodeDelay = Param.Unsigned("Commit to decode delay") - fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") - decodeWidth = Param.Unsigned("Decode width") - - iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " - "delay") - commitToRenameDelay = Param.Unsigned("Commit to rename delay") - decodeToRenameDelay = Param.Unsigned("Decode to rename delay") - renameWidth = Param.Unsigned("Rename width") - - commitToIEWDelay = Param.Unsigned("Commit to " - "Issue/Execute/Writeback delay") - renameToIEWDelay = Param.Unsigned("Rename to " - "Issue/Execute/Writeback delay") - issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " - "to the IEW stage)") - issueWidth = Param.Unsigned("Issue width") - executeWidth = Param.Unsigned("Execute width") - executeIntWidth = Param.Unsigned("Integer execute width") - executeFloatWidth = Param.Unsigned("Floating point execute width") - executeBranchWidth = Param.Unsigned("Branch execute width") - executeMemoryWidth = Param.Unsigned("Memory execute width") - - iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " - "delay") - renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") - commitWidth = Param.Unsigned("Commit width") - squashWidth = Param.Unsigned("Squash width") - - local_predictor_size = Param.Unsigned("Size of local predictor") - local_ctr_bits = Param.Unsigned("Bits per counter") - local_history_table_size = Param.Unsigned("Size of local history table") - local_history_bits = Param.Unsigned("Bits for the local history") - global_predictor_size = Param.Unsigned("Size of global predictor") - global_ctr_bits = Param.Unsigned("Bits per counter") - global_history_bits = Param.Unsigned("Bits of history") - choice_predictor_size = Param.Unsigned("Size of choice predictor") - choice_ctr_bits = Param.Unsigned("Bits of choice counters") - - BTBEntries = Param.Unsigned("Number of BTB entries") - BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") - - RASSize = Param.Unsigned("RAS size") - - LQEntries = Param.Unsigned("Number of load queue entries") - SQEntries = Param.Unsigned("Number of store queue entries") - LFSTSize = Param.Unsigned("Last fetched store table size") - SSITSize = Param.Unsigned("Store set ID table size") - - numPhysIntRegs = Param.Unsigned("Number of physical integer registers") - numPhysFloatRegs = Param.Unsigned("Number of physical floating point " - "registers") - numIQEntries = Param.Unsigned("Number of instruction queue entries") - numROBEntries = Param.Unsigned("Number of reorder buffer entries") - - instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") - - function_trace = Param.Bool(False, "Enable function trace") - function_trace_start = Param.Tick(0, "Cycle to start function trace") diff --git a/python/m5/objects/AlphaFullCPU.py b/python/m5/objects/AlphaFullCPU.py new file mode 100644 index 000000000..48989d057 --- /dev/null +++ b/python/m5/objects/AlphaFullCPU.py @@ -0,0 +1,80 @@ +from m5 import * +from BaseCPU import BaseCPU + +class DerivAlphaFullCPU(BaseCPU): + type = 'DerivAlphaFullCPU' + + numThreads = Param.Unsigned("number of HW thread contexts") + + if not build_env['FULL_SYSTEM']: + mem = Param.FunctionalMemory(NULL, "memory") + + decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") + renameToFetchDelay = Param.Unsigned("Rename to fetch delay") + iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " + "delay") + commitToFetchDelay = Param.Unsigned("Commit to fetch delay") + fetchWidth = Param.Unsigned("Fetch width") + + renameToDecodeDelay = Param.Unsigned("Rename to decode delay") + iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " + "delay") + commitToDecodeDelay = Param.Unsigned("Commit to decode delay") + fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") + decodeWidth = Param.Unsigned("Decode width") + + iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " + "delay") + commitToRenameDelay = Param.Unsigned("Commit to rename delay") + decodeToRenameDelay = Param.Unsigned("Decode to rename delay") + renameWidth = Param.Unsigned("Rename width") + + commitToIEWDelay = Param.Unsigned("Commit to " + "Issue/Execute/Writeback delay") + renameToIEWDelay = Param.Unsigned("Rename to " + "Issue/Execute/Writeback delay") + issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " + "to the IEW stage)") + issueWidth = Param.Unsigned("Issue width") + executeWidth = Param.Unsigned("Execute width") + executeIntWidth = Param.Unsigned("Integer execute width") + executeFloatWidth = Param.Unsigned("Floating point execute width") + executeBranchWidth = Param.Unsigned("Branch execute width") + executeMemoryWidth = Param.Unsigned("Memory execute width") + + iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " + "delay") + renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") + commitWidth = Param.Unsigned("Commit width") + squashWidth = Param.Unsigned("Squash width") + + local_predictor_size = Param.Unsigned("Size of local predictor") + local_ctr_bits = Param.Unsigned("Bits per counter") + local_history_table_size = Param.Unsigned("Size of local history table") + local_history_bits = Param.Unsigned("Bits for the local history") + global_predictor_size = Param.Unsigned("Size of global predictor") + global_ctr_bits = Param.Unsigned("Bits per counter") + global_history_bits = Param.Unsigned("Bits of history") + choice_predictor_size = Param.Unsigned("Size of choice predictor") + choice_ctr_bits = Param.Unsigned("Bits of choice counters") + + BTBEntries = Param.Unsigned("Number of BTB entries") + BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") + + RASSize = Param.Unsigned("RAS size") + + LQEntries = Param.Unsigned("Number of load queue entries") + SQEntries = Param.Unsigned("Number of store queue entries") + LFSTSize = Param.Unsigned("Last fetched store table size") + SSITSize = Param.Unsigned("Store set ID table size") + + numPhysIntRegs = Param.Unsigned("Number of physical integer registers") + numPhysFloatRegs = Param.Unsigned("Number of physical floating point " + "registers") + numIQEntries = Param.Unsigned("Number of instruction queue entries") + numROBEntries = Param.Unsigned("Number of reorder buffer entries") + + instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") + + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") diff --git a/python/m5/objects/AlphaTLB.mpy b/python/m5/objects/AlphaTLB.mpy deleted file mode 100644 index 8e7cd62cc..000000000 --- a/python/m5/objects/AlphaTLB.mpy +++ /dev/null @@ -1,12 +0,0 @@ -simobj AlphaTLB(SimObject): - type = 'AlphaTLB' - abstract = True - size = Param.Int("TLB size") - -simobj AlphaDTB(AlphaTLB): - type = 'AlphaDTB' - size = 64 - -simobj AlphaITB(AlphaTLB): - type = 'AlphaITB' - size = 48 diff --git a/python/m5/objects/AlphaTLB.py b/python/m5/objects/AlphaTLB.py new file mode 100644 index 000000000..5edf8e13d --- /dev/null +++ b/python/m5/objects/AlphaTLB.py @@ -0,0 +1,13 @@ +from m5 import * +class AlphaTLB(SimObject): + type = 'AlphaTLB' + abstract = True + size = Param.Int("TLB size") + +class AlphaDTB(AlphaTLB): + type = 'AlphaDTB' + size = 64 + +class AlphaITB(AlphaTLB): + type = 'AlphaITB' + size = 48 diff --git a/python/m5/objects/BadDevice.mpy b/python/m5/objects/BadDevice.mpy deleted file mode 100644 index 35a12e0bf..000000000 --- a/python/m5/objects/BadDevice.mpy +++ /dev/null @@ -1,5 +0,0 @@ -from Device import PioDevice - -simobj BadDevice(PioDevice): - type = 'BadDevice' - devicename = Param.String("Name of device to error on") diff --git a/python/m5/objects/BadDevice.py b/python/m5/objects/BadDevice.py new file mode 100644 index 000000000..3fba4637d --- /dev/null +++ b/python/m5/objects/BadDevice.py @@ -0,0 +1,6 @@ +from m5 import * +from Device import PioDevice + +class BadDevice(PioDevice): + type = 'BadDevice' + devicename = Param.String("Name of device to error on") diff --git a/python/m5/objects/BaseCPU.mpy b/python/m5/objects/BaseCPU.mpy deleted file mode 100644 index 707d1b94f..000000000 --- a/python/m5/objects/BaseCPU.mpy +++ /dev/null @@ -1,27 +0,0 @@ -simobj BaseCPU(SimObject): - type = 'BaseCPU' - abstract = True - icache = Param.BaseMem(NULL, "L1 instruction cache object") - dcache = Param.BaseMem(NULL, "L1 data cache object") - - if build_env['FULL_SYSTEM']: - dtb = Param.AlphaDTB("Data TLB") - itb = Param.AlphaITB("Instruction TLB") - mem = Param.FunctionalMemory("memory") - system = Param.BaseSystem(parent.any, "system object") - else: - workload = VectorParam.Process("processes to run") - - max_insts_all_threads = Param.Counter(0, - "terminate when all threads have reached this inst count") - max_insts_any_thread = Param.Counter(0, - "terminate when any thread reaches this inst count") - max_loads_all_threads = Param.Counter(0, - "terminate when all threads have reached this load count") - max_loads_any_thread = Param.Counter(0, - "terminate when any thread reaches this load count") - - defer_registration = Param.Bool(False, - "defer registration with system (for sampling)") - - cycle_time = Param.ClockPeriod(parent.frequency, "clock speed") diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py new file mode 100644 index 000000000..d4fa13d3b --- /dev/null +++ b/python/m5/objects/BaseCPU.py @@ -0,0 +1,28 @@ +from m5 import * +class BaseCPU(SimObject): + type = 'BaseCPU' + abstract = True + icache = Param.BaseMem(NULL, "L1 instruction cache object") + dcache = Param.BaseMem(NULL, "L1 data cache object") + + if build_env['FULL_SYSTEM']: + dtb = Param.AlphaDTB("Data TLB") + itb = Param.AlphaITB("Instruction TLB") + mem = Param.FunctionalMemory("memory") + system = Param.BaseSystem(Parent.any, "system object") + else: + workload = VectorParam.Process("processes to run") + + max_insts_all_threads = Param.Counter(0, + "terminate when all threads have reached this inst count") + max_insts_any_thread = Param.Counter(0, + "terminate when any thread reaches this inst count") + max_loads_all_threads = Param.Counter(0, + "terminate when all threads have reached this load count") + max_loads_any_thread = Param.Counter(0, + "terminate when any thread reaches this load count") + + defer_registration = Param.Bool(False, + "defer registration with system (for sampling)") + + cycle_time = Param.Latency(Parent.frequency.latency, "clock speed") diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy deleted file mode 100644 index a9a665f77..000000000 --- a/python/m5/objects/BaseCache.mpy +++ /dev/null @@ -1,64 +0,0 @@ -from BaseMem import BaseMem - -class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] - -simobj BaseCache(BaseMem): - type = 'BaseCache' - adaptive_compression = Param.Bool(False, - "Use an adaptive compression scheme") - assoc = Param.Int("associativity") - block_size = Param.Int("block size in bytes") - compressed_bus = Param.Bool(False, - "This cache connects to a compressed memory") - compression_latency = Param.Latency('0c', - "Latency in cycles of compression algorithm") - do_copy = Param.Bool(False, "perform fast copies in the cache") - hash_delay = Param.Int(1, "time in cycles of hash access") - in_bus = Param.Bus(NULL, "incoming bus object") - lifo = Param.Bool(False, - "whether this NIC partition should use LIFO repl. policy") - max_miss_count = Param.Counter(0, - "number of misses to handle before calling exit") - mem_trace = Param.MemTraceWriter(NULL, - "memory trace writer to record accesses") - mshrs = Param.Int("number of MSHRs (max outstanding requests)") - out_bus = Param.Bus("outgoing bus object") - prioritizeRequests = Param.Bool(False, - "always service demand misses first") - protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") - repl = Param.Repl(NULL, "replacement policy") - size = Param.MemorySize("capacity in bytes") - split = Param.Bool(False, "whether or not this cache is split") - split_size = Param.Int(0, - "How many ways of the cache belong to CPU/LRU partition") - store_compressed = Param.Bool(False, - "Store compressed data in the cache") - subblock_size = Param.Int(0, - "Size of subblock in IIC used for compression") - tgts_per_mshr = Param.Int("max number of accesses per MSHR") - trace_addr = Param.Addr(0, "address to trace") - two_queue = Param.Bool(False, - "whether the lifo should have two queue replacement") - write_buffers = Param.Int(8, "number of write buffers") - prefetch_miss = Param.Bool(False, - "wheter you are using the hardware prefetcher from Miss stream") - prefetch_access = Param.Bool(False, - "wheter you are using the hardware prefetcher from Access stream") - prefetcher_size = Param.Int(100, - "Number of entries in the harware prefetch queue") - prefetch_past_page = Param.Bool(False, - "Allow prefetches to cross virtual page boundaries") - prefetch_serial_squash = Param.Bool(False, - "Squash prefetches with a later time on a subsequent miss") - prefetch_degree = Param.Int(1, - "Degree of the prefetch depth") - prefetch_latency = Param.Tick(10, - "Latency of the prefetcher") - prefetch_policy = Param.Prefetch('none', - "Type of prefetcher to use") - prefetch_cache_check_push = Param.Bool(True, - "Check if in cash on push or pop of prefetch queue") - prefetch_use_cpu_id = Param.Bool(True, - "Use the CPU ID to seperate calculations of prefetches") - prefetch_data_accesses_only = Param.Bool(False, - "Only prefetch on data not on instruction accesses") diff --git a/python/m5/objects/BaseCache.py b/python/m5/objects/BaseCache.py new file mode 100644 index 000000000..d311969fa --- /dev/null +++ b/python/m5/objects/BaseCache.py @@ -0,0 +1,65 @@ +from m5 import * +from BaseMem import BaseMem + +class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] + +class BaseCache(BaseMem): + type = 'BaseCache' + adaptive_compression = Param.Bool(False, + "Use an adaptive compression scheme") + assoc = Param.Int("associativity") + block_size = Param.Int("block size in bytes") + compressed_bus = Param.Bool(False, + "This cache connects to a compressed memory") + compression_latency = Param.Latency(0, + "Latency in cycles of compression algorithm") + do_copy = Param.Bool(False, "perform fast copies in the cache") + hash_delay = Param.Int(1, "time in cycles of hash access") + in_bus = Param.Bus(NULL, "incoming bus object") + lifo = Param.Bool(False, + "whether this NIC partition should use LIFO repl. policy") + max_miss_count = Param.Counter(0, + "number of misses to handle before calling exit") + mem_trace = Param.MemTraceWriter(NULL, + "memory trace writer to record accesses") + mshrs = Param.Int("number of MSHRs (max outstanding requests)") + out_bus = Param.Bus("outgoing bus object") + prioritizeRequests = Param.Bool(False, + "always service demand misses first") + protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") + repl = Param.Repl(NULL, "replacement policy") + size = Param.MemorySize("capacity in bytes") + split = Param.Bool(False, "whether or not this cache is split") + split_size = Param.Int(0, + "How many ways of the cache belong to CPU/LRU partition") + store_compressed = Param.Bool(False, + "Store compressed data in the cache") + subblock_size = Param.Int(0, + "Size of subblock in IIC used for compression") + tgts_per_mshr = Param.Int("max number of accesses per MSHR") + trace_addr = Param.Addr(0, "address to trace") + two_queue = Param.Bool(False, + "whether the lifo should have two queue replacement") + write_buffers = Param.Int(8, "number of write buffers") + prefetch_miss = Param.Bool(False, + "wheter you are using the hardware prefetcher from Miss stream") + prefetch_access = Param.Bool(False, + "wheter you are using the hardware prefetcher from Access stream") + prefetcher_size = Param.Int(100, + "Number of entries in the harware prefetch queue") + prefetch_past_page = Param.Bool(False, + "Allow prefetches to cross virtual page boundaries") + prefetch_serial_squash = Param.Bool(False, + "Squash prefetches with a later time on a subsequent miss") + prefetch_degree = Param.Int(1, + "Degree of the prefetch depth") + prefetch_latency = Param.Tick(10, + "Latency of the prefetcher") + prefetch_policy = Param.Prefetch('none', + "Type of prefetcher to use") + prefetch_cache_check_push = Param.Bool(True, + "Check if in cash on push or pop of prefetch queue") + prefetch_use_cpu_id = Param.Bool(True, + "Use the CPU ID to seperate calculations of prefetches") + prefetch_data_accesses_only = Param.Bool(False, + "Only prefetch on data not on instruction accesses") diff --git a/python/m5/objects/BaseSystem.mpy b/python/m5/objects/BaseSystem.mpy deleted file mode 100644 index 29fe3e1d9..000000000 --- a/python/m5/objects/BaseSystem.mpy +++ /dev/null @@ -1,17 +0,0 @@ -simobj BaseSystem(SimObject): - type = 'BaseSystem' - abstract = True - boot_cpu_frequency = Param.ClockPeriod(parent.cpu[0].cycle_time, - "Boot Processor Frequency") - memctrl = Param.MemoryController(parent.any, "memory controller") - physmem = Param.PhysicalMemory(parent.any, "phsyical memory") - kernel = Param.String("file that contains the kernel code") - console = Param.String("file that contains the console code") - pal = Param.String("file that contains palcode") - readfile = Param.String("", "file to read startup script from") - init_param = Param.UInt64(0, "numerical value to pass into simulator") - boot_osflags = Param.String("a", "boot flags to pass to the kernel") - system_type = Param.UInt64("Type of system we are emulating") - system_rev = Param.UInt64("Revision of system we are emulating") - bin = Param.Bool(False, "is this system binned") - binned_fns = VectorParam.String([], "functions broken down and binned") diff --git a/python/m5/objects/BaseSystem.py b/python/m5/objects/BaseSystem.py new file mode 100644 index 000000000..48c70e44f --- /dev/null +++ b/python/m5/objects/BaseSystem.py @@ -0,0 +1,18 @@ +from m5 import * +class BaseSystem(SimObject): + type = 'BaseSystem' + abstract = True + boot_cpu_frequency = Param.Frequency(Self.cpu[0].cycle_time.frequency, + "boot processor frequency") + memctrl = Param.MemoryController(Parent.any, "memory controller") + physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") + kernel = Param.String("file that contains the kernel code") + console = Param.String("file that contains the console code") + pal = Param.String("file that contains palcode") + readfile = Param.String("", "file to read startup script from") + init_param = Param.UInt64(0, "numerical value to pass into simulator") + boot_osflags = Param.String("a", "boot flags to pass to the kernel") + system_type = Param.UInt64("Type of system we are emulating") + system_rev = Param.UInt64("Revision of system we are emulating") + bin = Param.Bool(False, "is this system binned") + binned_fns = VectorParam.String([], "functions broken down and binned") diff --git a/python/m5/objects/Bus.mpy b/python/m5/objects/Bus.mpy deleted file mode 100644 index aa12f757a..000000000 --- a/python/m5/objects/Bus.mpy +++ /dev/null @@ -1,6 +0,0 @@ -from BaseHier import BaseHier - -simobj Bus(BaseHier): - type = 'Bus' - clock_ratio = Param.ClockPeriod("ratio of CPU to bus frequency") - width = Param.Int("bus width in bytes") diff --git a/python/m5/objects/Bus.py b/python/m5/objects/Bus.py new file mode 100644 index 000000000..1ed87d2e7 --- /dev/null +++ b/python/m5/objects/Bus.py @@ -0,0 +1,7 @@ +from m5 import * +from BaseHier import BaseHier + +class Bus(BaseHier): + type = 'Bus' + clock_ratio = Param.Frequency("ratio of CPU to bus frequency") + width = Param.Int("bus width in bytes") diff --git a/python/m5/objects/CoherenceProtocol.mpy b/python/m5/objects/CoherenceProtocol.mpy deleted file mode 100644 index f3b0026b7..000000000 --- a/python/m5/objects/CoherenceProtocol.mpy +++ /dev/null @@ -1,6 +0,0 @@ -class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi'] - -simobj CoherenceProtocol(SimObject): - type = 'CoherenceProtocol' - do_upgrades = Param.Bool(True, "use upgrade transactions?") - protocol = Param.Coherence("name of coherence protocol") diff --git a/python/m5/objects/CoherenceProtocol.py b/python/m5/objects/CoherenceProtocol.py new file mode 100644 index 000000000..7013000d6 --- /dev/null +++ b/python/m5/objects/CoherenceProtocol.py @@ -0,0 +1,7 @@ +from m5 import * +class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi'] + +class CoherenceProtocol(SimObject): + type = 'CoherenceProtocol' + do_upgrades = Param.Bool(True, "use upgrade transactions?") + protocol = Param.Coherence("name of coherence protocol") diff --git a/python/m5/objects/Device.mpy b/python/m5/objects/Device.mpy deleted file mode 100644 index a0d02a647..000000000 --- a/python/m5/objects/Device.mpy +++ /dev/null @@ -1,33 +0,0 @@ -from FunctionalMemory import FunctionalMemory - -# This device exists only because there are some devices that I don't -# want to have a Platform parameter because it would cause a cycle in -# the C++ that cannot be easily solved. -# -# The real solution to this problem is to pass the ParamXXX structure -# to the constructor, but with the express condition that SimObject -# parameter values are not to be available at construction time. If -# some further configuration must be done, it must be done during the -# initialization phase at which point all SimObject pointers will be -# valid. -simobj FooPioDevice(FunctionalMemory): - type = 'PioDevice' - abstract = True - addr = Param.Addr("Device Address") - mmu = Param.MemoryController(parent.any, "Memory Controller") - io_bus = Param.Bus(NULL, "The IO Bus to attach to") - pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles") - -simobj FooDmaDevice(FooPioDevice): - type = 'DmaDevice' - abstract = True - -simobj PioDevice(FooPioDevice): - type = 'PioDevice' - abstract = True - platform = Param.Platform(parent.any, "Platform") - -simobj DmaDevice(PioDevice): - type = 'DmaDevice' - abstract = True - diff --git a/python/m5/objects/Device.py b/python/m5/objects/Device.py new file mode 100644 index 000000000..7f6ccd3e7 --- /dev/null +++ b/python/m5/objects/Device.py @@ -0,0 +1,34 @@ +from m5 import * +from FunctionalMemory import FunctionalMemory + +# This device exists only because there are some devices that I don't +# want to have a Platform parameter because it would cause a cycle in +# the C++ that cannot be easily solved. +# +# The real solution to this problem is to pass the ParamXXX structure +# to the constructor, but with the express condition that SimObject +# parameter values are not to be available at construction time. If +# some further configuration must be done, it must be done during the +# initialization phase at which point all SimObject pointers will be +# valid. +class FooPioDevice(FunctionalMemory): + type = 'PioDevice' + abstract = True + addr = Param.Addr("Device Address") + mmu = Param.MemoryController(Parent.any, "Memory Controller") + io_bus = Param.Bus(NULL, "The IO Bus to attach to") + pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles") + +class FooDmaDevice(FooPioDevice): + type = 'DmaDevice' + abstract = True + +class PioDevice(FooPioDevice): + type = 'PioDevice' + abstract = True + platform = Param.Platform(Parent.any, "Platform") + +class DmaDevice(PioDevice): + type = 'DmaDevice' + abstract = True + diff --git a/python/m5/objects/DiskImage.mpy b/python/m5/objects/DiskImage.mpy deleted file mode 100644 index 80ef7b072..000000000 --- a/python/m5/objects/DiskImage.mpy +++ /dev/null @@ -1,14 +0,0 @@ -simobj DiskImage(SimObject): - type = 'DiskImage' - abstract = True - image_file = Param.String("disk image file") - read_only = Param.Bool(False, "read only image") - -simobj RawDiskImage(DiskImage): - type = 'RawDiskImage' - -simobj CowDiskImage(DiskImage): - type = 'CowDiskImage' - child = Param.DiskImage("child image") - table_size = Param.Int(65536, "initial table size") - image_file = '' diff --git a/python/m5/objects/DiskImage.py b/python/m5/objects/DiskImage.py new file mode 100644 index 000000000..0d55e9329 --- /dev/null +++ b/python/m5/objects/DiskImage.py @@ -0,0 +1,15 @@ +from m5 import * +class DiskImage(SimObject): + type = 'DiskImage' + abstract = True + image_file = Param.String("disk image file") + read_only = Param.Bool(False, "read only image") + +class RawDiskImage(DiskImage): + type = 'RawDiskImage' + +class CowDiskImage(DiskImage): + type = 'CowDiskImage' + child = Param.DiskImage("child image") + table_size = Param.Int(65536, "initial table size") + image_file = '' diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy deleted file mode 100644 index 0065a238f..000000000 --- a/python/m5/objects/Ethernet.mpy +++ /dev/null @@ -1,121 +0,0 @@ -from Device import DmaDevice -from Pci import PciDevice - -simobj EtherInt(SimObject): - type = 'EtherInt' - abstract = True - peer = Param.EtherInt(NULL, "peer interface") - -simobj EtherLink(SimObject): - type = 'EtherLink' - int1 = Param.EtherInt("interface 1") - int2 = Param.EtherInt("interface 2") - delay = Param.Latency('0us', "packet transmit delay") - speed = Param.NetworkBandwidth('100Mbps', "link speed") - dump = Param.EtherDump(NULL, "dump object") - -simobj EtherBus(SimObject): - type = 'EtherBus' - loopback = Param.Bool(True, "send packet back to the sending interface") - dump = Param.EtherDump(NULL, "dump object") - speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") - -simobj EtherTap(EtherInt): - type = 'EtherTap' - bufsz = Param.Int(10000, "tap buffer size") - dump = Param.EtherDump(NULL, "dump object") - port = Param.UInt16(3500, "tap port") - -simobj EtherDump(SimObject): - type = 'EtherDump' - file = Param.String("dump file") - -simobj EtherDev(DmaDevice): - type = 'EtherDev' - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") - dma_read_factor = Param.Latency('0us', "multiplier for dma reads") - dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") - dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - rx_delay = Param.Latency('1us', "Receive Delay") - tx_delay = Param.Latency('1us', "Transmit Delay") - - intr_delay = Param.Latency('0us', "Interrupt Delay") - payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(parent.any, "Physical Memory") - tlaser = Param.Turbolaser(parent.any, "Turbolaser") - -simobj NSGigE(PciDevice): - type = 'NSGigE' - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - cycle_time = Param.Frequency('100MHz', "State machine processor frequency") - - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") - dma_read_factor = Param.Latency('0us', "multiplier for dma reads") - dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") - dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") - - - rx_filter = Param.Bool(True, "Enable Receive Filter") - rx_delay = Param.Latency('1us', "Receive Delay") - tx_delay = Param.Latency('1us', "Transmit Delay") - - rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo") - tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo") - - m5reg = Param.UInt32(0, "Register for m5 usage") - - intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds") - payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(parent.any, "Physical Memory") - -simobj EtherDevInt(EtherInt): - type = 'EtherDevInt' - device = Param.EtherDev("Ethernet device of this interface") - -simobj NSGigEInt(EtherInt): - type = 'NSGigEInt' - device = Param.NSGigE("Ethernet device of this interface") - -simobj Sinic(PciDevice): - type = 'Sinic' - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - cycle_time = Param.Frequency('100MHz', "State machine processor frequency") - - dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") - dma_read_factor = Param.Latency('0us', "multiplier for dma reads") - dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") - dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - rx_delay = Param.Latency('1us', "Receive Delay") - tx_delay = Param.Latency('1us', "Transmit Delay") - - rx_max_copy = Param.MemorySize('16kB', "rx max copy") - tx_max_copy = Param.MemorySize('16kB', "tx max copy") - rx_fifo_size = Param.MemorySize('64kB', "max size of rx fifo") - tx_fifo_size = Param.MemorySize('64kB', "max size of tx fifo") - rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold") - tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold") - - intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds") - payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(parent.any, "Physical Memory") - -simobj SinicInt(EtherInt): - type = 'SinicInt' - device = Param.Sinic("Ethernet device of this interface") diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py new file mode 100644 index 000000000..69dec1528 --- /dev/null +++ b/python/m5/objects/Ethernet.py @@ -0,0 +1,122 @@ +from m5 import * +from Device import DmaDevice +from Pci import PciDevice + +class EtherInt(SimObject): + type = 'EtherInt' + abstract = True + peer = Param.EtherInt(NULL, "peer interface") + +class EtherLink(SimObject): + type = 'EtherLink' + int1 = Param.EtherInt("interface 1") + int2 = Param.EtherInt("interface 2") + delay = Param.Latency('0us', "packet transmit delay") + speed = Param.NetworkBandwidth('100Mbps', "link speed") + dump = Param.EtherDump(NULL, "dump object") + +class EtherBus(SimObject): + type = 'EtherBus' + loopback = Param.Bool(True, "send packet back to the sending interface") + dump = Param.EtherDump(NULL, "dump object") + speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") + +class EtherTap(EtherInt): + type = 'EtherTap' + bufsz = Param.Int(10000, "tap buffer size") + dump = Param.EtherDump(NULL, "dump object") + port = Param.UInt16(3500, "tap port") + +class EtherDump(SimObject): + type = 'EtherDump' + file = Param.String("dump file") + +class EtherDev(DmaDevice): + type = 'EtherDev' + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") + + dma_data_free = Param.Bool(False, "DMA of Data is free") + dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") + dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") + dma_read_factor = Param.Latency('0us', "multiplier for dma reads") + dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") + dma_write_factor = Param.Latency('0us', "multiplier for dma writes") + dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") + + rx_filter = Param.Bool(True, "Enable Receive Filter") + rx_delay = Param.Latency('1us', "Receive Delay") + tx_delay = Param.Latency('1us', "Transmit Delay") + + intr_delay = Param.Latency('0us', "Interrupt Delay") + payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") + physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") + tlaser = Param.Turbolaser(Parent.any, "Turbolaser") + +class NSGigE(PciDevice): + type = 'NSGigE' + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") + + cycle_time = Param.Frequency('100MHz', "State machine processor frequency") + + dma_data_free = Param.Bool(False, "DMA of Data is free") + dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") + dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") + dma_read_factor = Param.Latency('0us', "multiplier for dma reads") + dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") + dma_write_factor = Param.Latency('0us', "multiplier for dma writes") + dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") + + + rx_filter = Param.Bool(True, "Enable Receive Filter") + rx_delay = Param.Latency('1us', "Receive Delay") + tx_delay = Param.Latency('1us', "Transmit Delay") + + rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo") + tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo") + + m5reg = Param.UInt32(0, "Register for m5 usage") + + intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds") + payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") + physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") + +class EtherDevInt(EtherInt): + type = 'EtherDevInt' + device = Param.EtherDev("Ethernet device of this interface") + +class NSGigEInt(EtherInt): + type = 'NSGigEInt' + device = Param.NSGigE("Ethernet device of this interface") + +class Sinic(PciDevice): + type = 'Sinic' + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") + + cycle_time = Param.Frequency('100MHz', "State machine processor frequency") + + dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") + dma_read_factor = Param.Latency('0us', "multiplier for dma reads") + dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") + dma_write_factor = Param.Latency('0us', "multiplier for dma writes") + + rx_filter = Param.Bool(True, "Enable Receive Filter") + rx_delay = Param.Latency('1us', "Receive Delay") + tx_delay = Param.Latency('1us', "Transmit Delay") + + rx_max_copy = Param.MemorySize('16kB', "rx max copy") + tx_max_copy = Param.MemorySize('16kB', "tx max copy") + rx_fifo_size = Param.MemorySize('64kB', "max size of rx fifo") + tx_fifo_size = Param.MemorySize('64kB', "max size of tx fifo") + rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold") + tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold") + + intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds") + payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") + physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") + +class SinicInt(EtherInt): + type = 'SinicInt' + device = Param.Sinic("Ethernet device of this interface") diff --git a/python/m5/objects/Ide.mpy b/python/m5/objects/Ide.mpy deleted file mode 100644 index 02b1d9567..000000000 --- a/python/m5/objects/Ide.mpy +++ /dev/null @@ -1,14 +0,0 @@ -from Pci import PciDevice - -class IdeID(Enum): vals = ['master', 'slave'] - -simobj IdeDisk(SimObject): - type = 'IdeDisk' - delay = Param.Latency('1us', "Fixed disk delay in microseconds") - driveID = Param.IdeID('master', "Drive ID") - image = Param.DiskImage("Disk image") - physmem = Param.PhysicalMemory(parent.any, "Physical memory") - -simobj IdeController(PciDevice): - type = 'IdeController' - disks = VectorParam.IdeDisk("IDE disks attached to this controller") diff --git a/python/m5/objects/Ide.py b/python/m5/objects/Ide.py new file mode 100644 index 000000000..6855ec653 --- /dev/null +++ b/python/m5/objects/Ide.py @@ -0,0 +1,15 @@ +from m5 import * +from Pci import PciDevice + +class IdeID(Enum): vals = ['master', 'slave'] + +class IdeDisk(SimObject): + type = 'IdeDisk' + delay = Param.Latency('1us', "Fixed disk delay in microseconds") + driveID = Param.IdeID('master', "Drive ID") + image = Param.DiskImage("Disk image") + physmem = Param.PhysicalMemory(Parent.any, "Physical memory") + +class IdeController(PciDevice): + type = 'IdeController' + disks = VectorParam.IdeDisk("IDE disks attached to this controller") diff --git a/python/m5/objects/IntrControl.mpy b/python/m5/objects/IntrControl.mpy deleted file mode 100644 index 144be0fd4..000000000 --- a/python/m5/objects/IntrControl.mpy +++ /dev/null @@ -1,3 +0,0 @@ -simobj IntrControl(SimObject): - type = 'IntrControl' - cpu = Param.BaseCPU(parent.any, "the cpu") diff --git a/python/m5/objects/IntrControl.py b/python/m5/objects/IntrControl.py new file mode 100644 index 000000000..66c82c182 --- /dev/null +++ b/python/m5/objects/IntrControl.py @@ -0,0 +1,4 @@ +from m5 import * +class IntrControl(SimObject): + type = 'IntrControl' + cpu = Param.BaseCPU(Parent.any, "the cpu") diff --git a/python/m5/objects/MemTest.mpy b/python/m5/objects/MemTest.mpy deleted file mode 100644 index af14ed9c3..000000000 --- a/python/m5/objects/MemTest.mpy +++ /dev/null @@ -1,18 +0,0 @@ -simobj MemTest(SimObject): - type = 'MemTest' - cache = Param.BaseCache("L1 cache") - check_mem = Param.FunctionalMemory("check memory") - main_mem = Param.FunctionalMemory("hierarchical memory") - max_loads = Param.Counter("number of loads to execute") - memory_size = Param.Int(65536, "memory size") - percent_copies = Param.Percent(0, "target copy percentage") - percent_dest_unaligned = Param.Percent(50, - "percent of copy dest address that are unaligned") - percent_reads = Param.Percent(65, "target read percentage") - percent_source_unaligned = Param.Percent(50, - "percent of copy source address that are unaligned") - percent_uncacheable = Param.Percent(10, - "target uncacheable percentage") - progress_interval = Param.Counter(1000000, - "progress report interval (in accesses)") - trace_addr = Param.Addr(0, "address to trace") diff --git a/python/m5/objects/MemTest.py b/python/m5/objects/MemTest.py new file mode 100644 index 000000000..34299faf0 --- /dev/null +++ b/python/m5/objects/MemTest.py @@ -0,0 +1,19 @@ +from m5 import * +class MemTest(SimObject): + type = 'MemTest' + cache = Param.BaseCache("L1 cache") + check_mem = Param.FunctionalMemory("check memory") + main_mem = Param.FunctionalMemory("hierarchical memory") + max_loads = Param.Counter("number of loads to execute") + memory_size = Param.Int(65536, "memory size") + percent_copies = Param.Percent(0, "target copy percentage") + percent_dest_unaligned = Param.Percent(50, + "percent of copy dest address that are unaligned") + percent_reads = Param.Percent(65, "target read percentage") + percent_source_unaligned = Param.Percent(50, + "percent of copy source address that are unaligned") + percent_uncacheable = Param.Percent(10, + "target uncacheable percentage") + progress_interval = Param.Counter(1000000, + "progress report interval (in accesses)") + trace_addr = Param.Addr(0, "address to trace") diff --git a/python/m5/objects/Pci.mpy b/python/m5/objects/Pci.mpy deleted file mode 100644 index b9b3e5a95..000000000 --- a/python/m5/objects/Pci.mpy +++ /dev/null @@ -1,51 +0,0 @@ -from Device import FooPioDevice, DmaDevice - -simobj PciConfigData(SimObject): - type = 'PciConfigData' - VendorID = Param.UInt16("Vendor ID") - DeviceID = Param.UInt16("Device ID") - Command = Param.UInt16(0, "Command") - Status = Param.UInt16(0, "Status") - Revision = Param.UInt8(0, "Device") - ProgIF = Param.UInt8(0, "Programming Interface") - SubClassCode = Param.UInt8(0, "Sub-Class Code") - ClassCode = Param.UInt8(0, "Class Code") - CacheLineSize = Param.UInt8(0, "System Cacheline Size") - LatencyTimer = Param.UInt8(0, "PCI Latency Timer") - HeaderType = Param.UInt8(0, "PCI Header Type") - BIST = Param.UInt8(0, "Built In Self Test") - - BAR0 = Param.UInt32(0x00, "Base Address Register 0") - BAR1 = Param.UInt32(0x00, "Base Address Register 1") - BAR2 = Param.UInt32(0x00, "Base Address Register 2") - BAR3 = Param.UInt32(0x00, "Base Address Register 3") - BAR4 = Param.UInt32(0x00, "Base Address Register 4") - BAR5 = Param.UInt32(0x00, "Base Address Register 5") - BAR0Size = Param.UInt32(0, "Base Address Register 0 Size") - BAR1Size = Param.UInt32(0, "Base Address Register 1 Size") - BAR2Size = Param.UInt32(0, "Base Address Register 2 Size") - BAR3Size = Param.UInt32(0, "Base Address Register 3 Size") - BAR4Size = Param.UInt32(0, "Base Address Register 4 Size") - BAR5Size = Param.UInt32(0, "Base Address Register 5 Size") - - CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") - SubsystemID = Param.UInt16(0x00, "Subsystem ID") - SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") - ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") - InterruptLine = Param.UInt8(0x00, "Interrupt Line") - InterruptPin = Param.UInt8(0x00, "Interrupt Pin") - MaximumLatency = Param.UInt8(0x00, "Maximum Latency") - MinimumGrant = Param.UInt8(0x00, "Minimum Grant") - -simobj PciConfigAll(FooPioDevice): - type = 'PciConfigAll' - -simobj PciDevice(DmaDevice): - type = 'PciDevice' - abstract = True - addr = 0xffffffffL - pci_bus = Param.Int("PCI bus") - pci_dev = Param.Int("PCI device number") - pci_func = Param.Int("PCI function code") - configdata = Param.PciConfigData(parent.any, "PCI Config data") - configspace = Param.PciConfigAll(parent.any, "PCI Configspace") diff --git a/python/m5/objects/Pci.py b/python/m5/objects/Pci.py new file mode 100644 index 000000000..0957e2883 --- /dev/null +++ b/python/m5/objects/Pci.py @@ -0,0 +1,52 @@ +from m5 import * +from Device import FooPioDevice, DmaDevice + +class PciConfigData(SimObject): + type = 'PciConfigData' + VendorID = Param.UInt16("Vendor ID") + DeviceID = Param.UInt16("Device ID") + Command = Param.UInt16(0, "Command") + Status = Param.UInt16(0, "Status") + Revision = Param.UInt8(0, "Device") + ProgIF = Param.UInt8(0, "Programming Interface") + SubClassCode = Param.UInt8(0, "Sub-Class Code") + ClassCode = Param.UInt8(0, "Class Code") + CacheLineSize = Param.UInt8(0, "System Cacheline Size") + LatencyTimer = Param.UInt8(0, "PCI Latency Timer") + HeaderType = Param.UInt8(0, "PCI Header Type") + BIST = Param.UInt8(0, "Built In Self Test") + + BAR0 = Param.UInt32(0x00, "Base Address Register 0") + BAR1 = Param.UInt32(0x00, "Base Address Register 1") + BAR2 = Param.UInt32(0x00, "Base Address Register 2") + BAR3 = Param.UInt32(0x00, "Base Address Register 3") + BAR4 = Param.UInt32(0x00, "Base Address Register 4") + BAR5 = Param.UInt32(0x00, "Base Address Register 5") + BAR0Size = Param.UInt32(0, "Base Address Register 0 Size") + BAR1Size = Param.UInt32(0, "Base Address Register 1 Size") + BAR2Size = Param.UInt32(0, "Base Address Register 2 Size") + BAR3Size = Param.UInt32(0, "Base Address Register 3 Size") + BAR4Size = Param.UInt32(0, "Base Address Register 4 Size") + BAR5Size = Param.UInt32(0, "Base Address Register 5 Size") + + CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") + SubsystemID = Param.UInt16(0x00, "Subsystem ID") + SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") + ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") + InterruptLine = Param.UInt8(0x00, "Interrupt Line") + InterruptPin = Param.UInt8(0x00, "Interrupt Pin") + MaximumLatency = Param.UInt8(0x00, "Maximum Latency") + MinimumGrant = Param.UInt8(0x00, "Minimum Grant") + +class PciConfigAll(FooPioDevice): + type = 'PciConfigAll' + +class PciDevice(DmaDevice): + type = 'PciDevice' + abstract = True + addr = 0xffffffffL + pci_bus = Param.Int("PCI bus") + pci_dev = Param.Int("PCI device number") + pci_func = Param.Int("PCI function code") + configdata = Param.PciConfigData(Parent.any, "PCI Config data") + configspace = Param.PciConfigAll(Parent.any, "PCI Configspace") diff --git a/python/m5/objects/PhysicalMemory.mpy b/python/m5/objects/PhysicalMemory.mpy deleted file mode 100644 index e6df2a161..000000000 --- a/python/m5/objects/PhysicalMemory.mpy +++ /dev/null @@ -1,7 +0,0 @@ -from FunctionalMemory import FunctionalMemory - -simobj PhysicalMemory(FunctionalMemory): - type = 'PhysicalMemory' - range = Param.AddrRange("Device Address") - file = Param.String('', "memory mapped file") - mmu = Param.MemoryController(parent.any, "Memory Controller") diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py new file mode 100644 index 000000000..f50937ee6 --- /dev/null +++ b/python/m5/objects/PhysicalMemory.py @@ -0,0 +1,8 @@ +from m5 import * +from FunctionalMemory import FunctionalMemory + +class PhysicalMemory(FunctionalMemory): + type = 'PhysicalMemory' + range = Param.AddrRange("Device Address") + file = Param.String('', "memory mapped file") + mmu = Param.MemoryController(Parent.any, "Memory Controller") diff --git a/python/m5/objects/Platform.mpy b/python/m5/objects/Platform.mpy deleted file mode 100644 index 166f3f4a1..000000000 --- a/python/m5/objects/Platform.mpy +++ /dev/null @@ -1,4 +0,0 @@ -simobj Platform(SimObject): - type = 'Platform' - abstract = True - intrctrl = Param.IntrControl(parent.any, "interrupt controller") diff --git a/python/m5/objects/Platform.py b/python/m5/objects/Platform.py new file mode 100644 index 000000000..4da0ffab4 --- /dev/null +++ b/python/m5/objects/Platform.py @@ -0,0 +1,5 @@ +from m5 import * +class Platform(SimObject): + type = 'Platform' + abstract = True + intrctrl = Param.IntrControl(Parent.any, "interrupt controller") diff --git a/python/m5/objects/Process.mpy b/python/m5/objects/Process.mpy deleted file mode 100644 index 6a91c09c2..000000000 --- a/python/m5/objects/Process.mpy +++ /dev/null @@ -1,15 +0,0 @@ -simobj Process(SimObject): - type = 'Process' - abstract = True - output = Param.String('cout', 'filename for stdout/stderr') - -simobj LiveProcess(Process): - type = 'LiveProcess' - cmd = VectorParam.String("command line (executable plus arguments)") - env = VectorParam.String('', "environment settings") - input = Param.String('cin', "filename for stdin") - -simobj EioProcess(Process): - type = 'EioProcess' - chkpt = Param.String('', "EIO checkpoint file name (optional)") - file = Param.String("EIO trace file name") diff --git a/python/m5/objects/Process.py b/python/m5/objects/Process.py new file mode 100644 index 000000000..17a66c6d9 --- /dev/null +++ b/python/m5/objects/Process.py @@ -0,0 +1,16 @@ +from m5 import * +class Process(SimObject): + type = 'Process' + abstract = True + output = Param.String('cout', 'filename for stdout/stderr') + +class LiveProcess(Process): + type = 'LiveProcess' + cmd = VectorParam.String("command line (executable plus arguments)") + env = VectorParam.String('', "environment settings") + input = Param.String('cin', "filename for stdin") + +class EioProcess(Process): + type = 'EioProcess' + chkpt = Param.String('', "EIO checkpoint file name (optional)") + file = Param.String("EIO trace file name") diff --git a/python/m5/objects/Repl.mpy b/python/m5/objects/Repl.mpy deleted file mode 100644 index fff5a2a02..000000000 --- a/python/m5/objects/Repl.mpy +++ /dev/null @@ -1,9 +0,0 @@ -simobj Repl(SimObject): - type = 'Repl' - abstract = True - -simobj GenRepl(Repl): - type = 'GenRepl' - fresh_res = Param.Int("associativity") - num_pools = Param.Int("capacity in bytes") - pool_res = Param.Int("block size in bytes") diff --git a/python/m5/objects/Repl.py b/python/m5/objects/Repl.py new file mode 100644 index 000000000..afd256082 --- /dev/null +++ b/python/m5/objects/Repl.py @@ -0,0 +1,10 @@ +from m5 import * +class Repl(SimObject): + type = 'Repl' + abstract = True + +class GenRepl(Repl): + type = 'GenRepl' + fresh_res = Param.Int("associativity") + num_pools = Param.Int("capacity in bytes") + pool_res = Param.Int("block size in bytes") diff --git a/python/m5/objects/Root.mpy b/python/m5/objects/Root.mpy deleted file mode 100644 index 2493dc4ff..000000000 --- a/python/m5/objects/Root.mpy +++ /dev/null @@ -1,14 +0,0 @@ -from HierParams import HierParams -from Serialize import Serialize -from Statistics import Statistics -from Trace import Trace - -simobj Root(SimObject): - type = 'Root' - frequency = Param.RootFrequency('200MHz', "tick frequency") - output_file = Param.String('cout', "file to dump simulator output to") - hier = HierParams(do_data = False, do_events = True) - checkpoint = Param.String('', "Checkpoint file") - stats = Statistics() - trace = Trace() - serialize = Serialize() diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py new file mode 100644 index 000000000..78d5388f0 --- /dev/null +++ b/python/m5/objects/Root.py @@ -0,0 +1,20 @@ +from m5 import * +from HierParams import HierParams +from Serialize import Serialize +from Statistics import Statistics +from Trace import Trace + +class Root(SimObject): + type = 'Root' + frequency = Param.RootFrequency('200MHz', "tick frequency") + output_file = Param.String('cout', "file to dump simulator output to") + checkpoint = Param.String('', "checkpoint file to load") +# hier = Param.HierParams(HierParams(do_data = False, do_events = True), +# "shared memory hierarchy parameters") +# stats = Param.Statistics(Statistics(), "statistics object") +# trace = Param.Trace(Trace(), "trace object") +# serialize = Param.Serialize(Serialize(), "checkpoint generation options") + hier = HierParams(do_data = False, do_events = True) + stats = Statistics() + trace = Trace() + serialize = Serialize() diff --git a/python/m5/objects/SimConsole.mpy b/python/m5/objects/SimConsole.mpy deleted file mode 100644 index 53ddaa25c..000000000 --- a/python/m5/objects/SimConsole.mpy +++ /dev/null @@ -1,11 +0,0 @@ -simobj ConsoleListener(SimObject): - type = 'ConsoleListener' - port = Param.TcpPort(3456, "listen port") - -simobj SimConsole(SimObject): - type = 'SimConsole' - append_name = Param.Bool(True, "append name() to filename") - intr_control = Param.IntrControl(parent.any, "interrupt controller") - listener = Param.ConsoleListener("console listener") - number = Param.Int(0, "console number") - output = Param.String('console', "file to dump output to") diff --git a/python/m5/objects/SimConsole.py b/python/m5/objects/SimConsole.py new file mode 100644 index 000000000..df3061908 --- /dev/null +++ b/python/m5/objects/SimConsole.py @@ -0,0 +1,12 @@ +from m5 import * +class ConsoleListener(SimObject): + type = 'ConsoleListener' + port = Param.TcpPort(3456, "listen port") + +class SimConsole(SimObject): + type = 'SimConsole' + append_name = Param.Bool(True, "append name() to filename") + intr_control = Param.IntrControl(Parent.any, "interrupt controller") + listener = Param.ConsoleListener("console listener") + number = Param.Int(0, "console number") + output = Param.String('console', "file to dump output to") diff --git a/python/m5/objects/SimpleDisk.mpy b/python/m5/objects/SimpleDisk.mpy deleted file mode 100644 index b616fb3d1..000000000 --- a/python/m5/objects/SimpleDisk.mpy +++ /dev/null @@ -1,4 +0,0 @@ -simobj SimpleDisk(SimObject): - type = 'SimpleDisk' - disk = Param.DiskImage("Disk Image") - physmem = Param.PhysicalMemory(parent.any, "Physical Memory") diff --git a/python/m5/objects/SimpleDisk.py b/python/m5/objects/SimpleDisk.py new file mode 100644 index 000000000..48448e6e5 --- /dev/null +++ b/python/m5/objects/SimpleDisk.py @@ -0,0 +1,5 @@ +from m5 import * +class SimpleDisk(SimObject): + type = 'SimpleDisk' + disk = Param.DiskImage("Disk Image") + physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") diff --git a/python/m5/objects/Tsunami.mpy b/python/m5/objects/Tsunami.mpy deleted file mode 100644 index c17eae121..000000000 --- a/python/m5/objects/Tsunami.mpy +++ /dev/null @@ -1,25 +0,0 @@ -from Device import FooPioDevice -from Platform import Platform - -simobj Tsunami(Platform): - type = 'Tsunami' - pciconfig = Param.PciConfigAll("PCI configuration") - system = Param.BaseSystem(parent.any, "system") - -simobj TsunamiCChip(FooPioDevice): - type = 'TsunamiCChip' - tsunami = Param.Tsunami(parent.any, "Tsunami") - -simobj TsunamiFake(FooPioDevice): - type = 'TsunamiFake' - -simobj TsunamiIO(FooPioDevice): - type = 'TsunamiIO' - time = Param.UInt64(1136073600, - "System time to use (0 for actual time, default is 1/1/06)") - tsunami = Param.Tsunami(parent.any, "Tsunami") - frequency = Param.Frequency('1024Hz', "frequency of interrupts") - -simobj TsunamiPChip(FooPioDevice): - type = 'TsunamiPChip' - tsunami = Param.Tsunami(parent.any, "Tsunami") diff --git a/python/m5/objects/Tsunami.py b/python/m5/objects/Tsunami.py new file mode 100644 index 000000000..fa3c18127 --- /dev/null +++ b/python/m5/objects/Tsunami.py @@ -0,0 +1,26 @@ +from m5 import * +from Device import FooPioDevice +from Platform import Platform + +class Tsunami(Platform): + type = 'Tsunami' + pciconfig = Param.PciConfigAll("PCI configuration") + system = Param.BaseSystem(Parent.any, "system") + +class TsunamiCChip(FooPioDevice): + type = 'TsunamiCChip' + tsunami = Param.Tsunami(Parent.any, "Tsunami") + +class TsunamiFake(FooPioDevice): + type = 'TsunamiFake' + +class TsunamiIO(FooPioDevice): + type = 'TsunamiIO' + time = Param.UInt64(1136073600, + "System time to use (0 for actual time, default is 1/1/06)") + tsunami = Param.Tsunami(Parent.any, "Tsunami") + frequency = Param.Frequency('1024Hz', "frequency of interrupts") + +class TsunamiPChip(FooPioDevice): + type = 'TsunamiPChip' + tsunami = Param.Tsunami(Parent.any, "Tsunami") diff --git a/python/m5/objects/Uart.mpy b/python/m5/objects/Uart.mpy deleted file mode 100644 index 5a6c25f8e..000000000 --- a/python/m5/objects/Uart.mpy +++ /dev/null @@ -1,6 +0,0 @@ -from Device import PioDevice - -simobj Uart(PioDevice): - type = 'Uart' - console = Param.SimConsole(parent.any, "The console") - size = Param.Addr(0x8, "Device size") diff --git a/python/m5/objects/Uart.py b/python/m5/objects/Uart.py new file mode 100644 index 000000000..cfb09acad --- /dev/null +++ b/python/m5/objects/Uart.py @@ -0,0 +1,7 @@ +from m5 import * +from Device import PioDevice + +class Uart(PioDevice): + type = 'Uart' + console = Param.SimConsole(Parent.any, "The console") + size = Param.Addr(0x8, "Device size") -- cgit v1.2.3