From 22504f8b48978be286d98be0df72d015ab6ff559 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 1 Mar 2006 18:45:50 -0500 Subject: More progress toward actually running a program. See configs/test.py for test config (using simple binary in my home directory on zizzer). base/chunk_generator.hh: Fix assertion for chunkSize == 0 (not a power of 2) base/intmath.hh: Fix roundDown to take integer alignments. cpu/base.cc: Register exec contexts regardless of state (not sure why this check was in here in the first place). mem/physical.cc: Add breaks to switch. python/m5/objects/BaseCPU.py: Default mem to Parent.any (e.g. get from System). python/m5/objects/Ethernet.py: python/m5/objects/Root.py: HierParams is gone. python/m5/objects/PhysicalMemory.py: mmu param is full-system only. sim/process.cc: Stack mapping request must be page-aligned and page-sized. Don't delete objFile object in create since we are counting on it being around for startup(). --HG-- extra : convert_revision : 90c43ee927e7d82a045d6e10302d965797d006f7 --- python/m5/objects/BaseCPU.py | 2 +- python/m5/objects/Ethernet.py | 1 - python/m5/objects/PhysicalMemory.py | 3 ++- python/m5/objects/Root.py | 4 ---- 4 files changed, 3 insertions(+), 7 deletions(-) (limited to 'python/m5') diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py index e5e43022f..07cb850f1 100644 --- a/python/m5/objects/BaseCPU.py +++ b/python/m5/objects/BaseCPU.py @@ -9,7 +9,7 @@ class BaseCPU(SimObject): system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") else: - mem = Param.Memory("memory") + mem = Param.Memory(Parent.any, "memory") workload = VectorParam.Process("processes to run") max_insts_all_threads = Param.Counter(0, diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index f58ece0be..2edc7576e 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -69,7 +69,6 @@ class EtherDevBase(PciDevice): physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") - hier = Param.HierParams(Parent.any, "Hierarchy global variables") payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") dma_read_factor = Param.Latency('0us', "multiplier for dma reads") diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py index ab2714a6f..b0aba1a7d 100644 --- a/python/m5/objects/PhysicalMemory.py +++ b/python/m5/objects/PhysicalMemory.py @@ -5,4 +5,5 @@ class PhysicalMemory(Memory): type = 'PhysicalMemory' range = Param.AddrRange("Device Address") file = Param.String('', "memory mapped file") - mmu = Param.MemoryController(Parent.any, "Memory Controller") + if build_env['FULL_SYSTEM']: + mmu = Param.MemoryController(Parent.any, "Memory Controller") diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py index 23b13fc67..f51516098 100644 --- a/python/m5/objects/Root.py +++ b/python/m5/objects/Root.py @@ -1,5 +1,4 @@ from m5 import * -from HierParams import HierParams from Serialize import Serialize from Statistics import Statistics from Trace import Trace @@ -13,12 +12,9 @@ class Root(SimObject): "print a progress message every n ticks (0 = never)") output_file = Param.String('cout', "file to dump simulator output to") checkpoint = Param.String('', "checkpoint file to load") -# hier = Param.HierParams(HierParams(do_data = False, do_events = True), -# "shared memory hierarchy parameters") # stats = Param.Statistics(Statistics(), "statistics object") # trace = Param.Trace(Trace(), "trace object") # serialize = Param.Serialize(Serialize(), "checkpoint generation options") - hier = HierParams(do_data = False, do_events = True) stats = Statistics() trace = Trace() exetrace = ExecutionTrace() -- cgit v1.2.3