From 4889d8f78826331d567327535fcd481fa2caf939 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Sat, 2 Apr 2005 20:36:08 -0500 Subject: Added support for multiple prefetch address from single access (depth of prefetch) also added the ability to squash some prefetchs to match the GHB technique python/m5/objects/BaseCache.mpy: Added parameters --HG-- extra : convert_revision : 92b646eb61455d283a5c2ac0b3f8fbd62e39fb87 --- python/m5/objects/BaseCache.mpy | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'python/m5') diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy index 198665325..3727f2f01 100644 --- a/python/m5/objects/BaseCache.mpy +++ b/python/m5/objects/BaseCache.mpy @@ -1,5 +1,7 @@ from BaseMem import BaseMem +class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] + simobj BaseCache(BaseMem): type = 'BaseCache' adaptive_compression = Param.Bool(False, @@ -44,4 +46,11 @@ simobj BaseCache(BaseMem): "Number of entries in the harware prefetch queue") prefetch_past_page = Param.Bool(False, "Allow prefetches to cross virtual page boundaries") - + prefetch_serial_squash = Param.Bool(False, + "Squash prefetches with a later time on a subsequent miss") + prefetch_degree = Param.Int(1, + "Degree of the prefetch depth") + prefetch_latency = Param.Tick(10, + "Latency of the prefetcher") + prefetch_policy = Param.Prefetch('none', + "Type of prefetcher to use") -- cgit v1.2.3 From 1b2c81b9d7835eb77b319e66bb8e0fb40f771b99 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Mon, 4 Apr 2005 16:25:22 -0400 Subject: Add more prefetcher support. SConscript: Add GHB prefetcher to build list python/m5/objects/BaseCache.mpy: Add parameters about when to remove prefetches and wether or not to use cpuid to differentiate access patterns --HG-- extra : convert_revision : 1d3fef21910f2f34b8c28d01b5f6e86eef53357c --- python/m5/objects/BaseCache.mpy | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'python/m5') diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy index 3727f2f01..214e0555c 100644 --- a/python/m5/objects/BaseCache.mpy +++ b/python/m5/objects/BaseCache.mpy @@ -54,3 +54,7 @@ simobj BaseCache(BaseMem): "Latency of the prefetcher") prefetch_policy = Param.Prefetch('none', "Type of prefetcher to use") + prefetch_cache_check_push = Param.Bool(True, + "Check if in cash on push or pop of prefetch queue") + prefetch_use_cpu_id = Param.Bool(True, + "Use the CPU ID to seperate calculations of prefetches") -- cgit v1.2.3 From c82562c7404287e22c4e83c45fa563fba0a14b0a Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 6 Apr 2005 16:58:40 -0400 Subject: full_system isn't a useful parameter anymore, get rid of it. python/m5/objects/Root.mpy: sim/universe.cc: util/stats/stats.py: full_system isn't a useful parameter --HG-- extra : convert_revision : 557091be1faa3cf121c55102aba4e6f4c1bd45ef --- python/m5/objects/Root.mpy | 1 - 1 file changed, 1 deletion(-) (limited to 'python/m5') diff --git a/python/m5/objects/Root.mpy b/python/m5/objects/Root.mpy index c535bd2dc..2493dc4ff 100644 --- a/python/m5/objects/Root.mpy +++ b/python/m5/objects/Root.mpy @@ -7,7 +7,6 @@ simobj Root(SimObject): type = 'Root' frequency = Param.RootFrequency('200MHz', "tick frequency") output_file = Param.String('cout', "file to dump simulator output to") - full_system = Param.Bool("Full system simulation?") hier = HierParams(do_data = False, do_events = True) checkpoint = Param.String('', "Checkpoint file") stats = Statistics() -- cgit v1.2.3 From 6d412f63a321ae1bd4247d9fdc0d4c34159d741c Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 6 Apr 2005 17:05:30 -0400 Subject: Add TcpPort and UdpPort as python types python/m5/objects/SimConsole.mpy: the listener port is a TcpPort --HG-- extra : convert_revision : c26fdd93d3bc35d9f1563ac1087a7f75471c9020 --- python/m5/config.py | 6 ++++-- python/m5/objects/SimConsole.mpy | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'python/m5') diff --git a/python/m5/config.py b/python/m5/config.py index a791bbebf..e744b9ffb 100644 --- a/python/m5/config.py +++ b/python/m5/config.py @@ -1140,8 +1140,10 @@ class UInt32(CheckedInt): cppname = 'uint32_t'; size = 32; unsigned = True class Int64(CheckedInt): cppname = 'int64_t'; size = 64; unsigned = False class UInt64(CheckedInt): cppname = 'uint64_t'; size = 64; unsigned = True -class Counter(CheckedInt): cppname = 'Counter'; size = 64; unsigned = True -class Tick(CheckedInt): cppname = 'Tick'; size = 64; unsigned = True +class Counter(CheckedInt): cppname = 'Counter'; size = 64; unsigned = True +class Tick(CheckedInt): cppname = 'Tick'; size = 64; unsigned = True +class TcpPort(CheckedInt): cppname = 'uint16_t'; size = 16; unsigned = True +class UdpPort(CheckedInt): cppname = 'uint16_t'; size = 16; unsigned = True class Percent(CheckedInt): cppname = 'int'; min = 0; max = 100 diff --git a/python/m5/objects/SimConsole.mpy b/python/m5/objects/SimConsole.mpy index 3588a949d..53ddaa25c 100644 --- a/python/m5/objects/SimConsole.mpy +++ b/python/m5/objects/SimConsole.mpy @@ -1,6 +1,6 @@ simobj ConsoleListener(SimObject): type = 'ConsoleListener' - port = Param.UInt16(3456, "listen port") + port = Param.TcpPort(3456, "listen port") simobj SimConsole(SimObject): type = 'SimConsole' -- cgit v1.2.3 From 1ee77fb23e12e6d75b4bc7395a244e9f19c7d0db Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 6 Apr 2005 17:58:57 -0400 Subject: formatting --HG-- extra : convert_revision : 0b041556222c3892ee72e4d56c8acdda72bfc303 --- python/m5/config.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'python/m5') diff --git a/python/m5/config.py b/python/m5/config.py index e744b9ffb..30ce340f6 100644 --- a/python/m5/config.py +++ b/python/m5/config.py @@ -1145,7 +1145,7 @@ class Tick(CheckedInt): cppname = 'Tick'; size = 64; unsigned = True class TcpPort(CheckedInt): cppname = 'uint16_t'; size = 16; unsigned = True class UdpPort(CheckedInt): cppname = 'uint16_t'; size = 16; unsigned = True -class Percent(CheckedInt): cppname = 'int'; min = 0; max = 100 +class Percent(CheckedInt): cppname = 'int'; min = 0; max = 100 class MemorySize(CheckedInt): cppname = 'uint64_t' -- cgit v1.2.3 From f3544a13f3559e1e51b1f039e6613d5c47e41fa8 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 6 Apr 2005 17:59:31 -0400 Subject: Fix the python NetworkBandwidth conversion function python/m5/convert.py: Fix the NetworkBandwidth conversion function --HG-- extra : convert_revision : 93d9856fe6b59827c116e15835d2ef51292bd6c4 --- python/m5/convert.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'python/m5') diff --git a/python/m5/convert.py b/python/m5/convert.py index 6ccefd2fc..a89303687 100644 --- a/python/m5/convert.py +++ b/python/m5/convert.py @@ -153,15 +153,15 @@ def toNetworkBandwidth(value): raise TypeError, "wrong type '%s' should be str" % type(value) if value.endswith('Tbps'): - return float(value[:-3]) * tera + return float(value[:-4]) * tera elif value.endswith('Gbps'): - return float(value[:-3]) * giga + return float(value[:-4]) * giga elif value.endswith('Mbps'): - return float(value[:-3]) * mega + return float(value[:-4]) * mega elif value.endswith('kbps'): - return float(value[:-3]) * kilo + return float(value[:-4]) * kilo elif value.endswith('bps'): - return float(value[:-2]) + return float(value[:-3]) else: return float(value) -- cgit v1.2.3 From 9fead747f5641021efc2bc240e62583607e8f06f Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 6 Apr 2005 18:00:44 -0400 Subject: fix typo in python config stuff python/m5/config.py: fix typo --HG-- extra : convert_revision : 2208453d93149ba4af140dd78c29be4c4943b397 --- python/m5/config.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'python/m5') diff --git a/python/m5/config.py b/python/m5/config.py index 30ce340f6..e260c57a7 100644 --- a/python/m5/config.py +++ b/python/m5/config.py @@ -1285,7 +1285,7 @@ class NullSimObject(object): pass def _convert(cls, value): - if value == Nxone: + if value == None: return if isinstance(value, cls): -- cgit v1.2.3