From 3e5e3e2d28a6a59df1300751f75f1de5b06bc3fe Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 5 Jun 2005 01:24:17 -0400 Subject: make all of the turbolaser stuff only compile if ALPHA_TLASER is defined. build/SConstruct: Default ALPHA_TLASER to false dev/uart8250.cc: fix paths --HG-- extra : convert_revision : 3616b5b4b9060860a73568a4ed4f1e8eb991938f --- python/m5/objects/Ethernet.py | 52 ++++++++++++++++++++++--------------------- python/m5/objects/Uart.py | 5 +++-- 2 files changed, 30 insertions(+), 27 deletions(-) (limited to 'python') diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index 61386a08d..2fbfb1138 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -31,27 +31,33 @@ class EtherDump(SimObject): type = 'EtherDump' file = Param.String("dump file") -class EtherDev(DmaDevice): - type = 'EtherDev' - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") - dma_read_factor = Param.Latency('0us', "multiplier for dma reads") - dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") - dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - rx_delay = Param.Latency('1us', "Receive Delay") - tx_delay = Param.Latency('1us', "Transmit Delay") - - intr_delay = Param.Latency('0us', "Interrupt Delay") - payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") - tlaser = Param.Turbolaser(Parent.any, "Turbolaser") +if build_env['ALPHA_TLASER']: + + class EtherDev(DmaDevice): + type = 'EtherDev' + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") + + dma_data_free = Param.Bool(False, "DMA of Data is free") + dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") + dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") + dma_read_factor = Param.Latency('0us', "multiplier for dma reads") + dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") + dma_write_factor = Param.Latency('0us', "multiplier for dma writes") + dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") + + rx_filter = Param.Bool(True, "Enable Receive Filter") + rx_delay = Param.Latency('1us', "Receive Delay") + tx_delay = Param.Latency('1us', "Transmit Delay") + + intr_delay = Param.Latency('0us', "Interrupt Delay") + payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") + physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") + tlaser = Param.Turbolaser(Parent.any, "Turbolaser") + + class EtherDevInt(EtherInt): + type = 'EtherDevInt' + device = Param.EtherDev("Ethernet device of this interface") class NSGigE(PciDevice): type = 'NSGigE' @@ -82,10 +88,6 @@ class NSGigE(PciDevice): payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") -class EtherDevInt(EtherInt): - type = 'EtherDevInt' - device = Param.EtherDev("Ethernet device of this interface") - class NSGigEInt(EtherInt): type = 'NSGigEInt' device = Param.NSGigE("Ethernet device of this interface") diff --git a/python/m5/objects/Uart.py b/python/m5/objects/Uart.py index 57b8b44af..6eda5cdb3 100644 --- a/python/m5/objects/Uart.py +++ b/python/m5/objects/Uart.py @@ -10,6 +10,7 @@ class Uart(PioDevice): class Uart8250(Uart): type = 'Uart8250' -class Uart8530(Uart): - type = 'Uart8530' +if build_env['ALPHA_TLASER']: + class Uart8530(Uart): + type = 'Uart8530' -- cgit v1.2.3