From c27c122afc6b778e67a9c77915fac71730a5a4ef Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sun, 26 Mar 2006 21:44:22 -0500 Subject: Add the bus and connector objects to scons change getPort parameter from char* to string Add an extra phase between construction and init called connect SConscript: Add the bus and connector objects to scons cpu/simple/cpu.cc: cpu/simple/cpu.hh: the connection to memory shouldn't be made until we know the memory object exists (e.g. after construction) dev/io_device.hh: change to const string mem/bus.hh: change getPort parameter from char* to string initialize num_interfaces mem/mem_object.hh: change getPort parameter from char* to string mem/physical.cc: mem/physical.hh: change getPort parameter from char* to string get rid of the bus object I created last time python/m5/objects/PhysicalMemory.py: get rid of the bus object I created last time sim/main.cc: sim/sim_object.cc: sim/sim_object.hh: Add an extra phase between construction and init called connect --HG-- extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9 --- sim/sim_object.cc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'sim/sim_object.cc') diff --git a/sim/sim_object.cc b/sim/sim_object.cc index f34e17fe6..151ba68a7 100644 --- a/sim/sim_object.cc +++ b/sim/sim_object.cc @@ -87,6 +87,11 @@ SimObject::SimObject(const string &_name) simObjectList.push_back(this); } +void +SimObject::connect() +{ +} + void SimObject::init() { @@ -150,6 +155,21 @@ SimObject::regAllStats() Stats::registerResetCallback(&StatResetCB); } +// +// static function: call connect() on all SimObjects. +// +void +SimObject::connectAll() +{ + SimObjectList::iterator i = simObjectList.begin(); + SimObjectList::iterator end = simObjectList.end(); + + for (; i != end; ++i) { + SimObject *obj = *i; + obj->connect(); + } +} + // // static function: call init() on all SimObjects. // -- cgit v1.2.3